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authorArthur Heymans <arthur@aheymans.xyz>2017-05-12 11:54:08 +0200
committerArthur Heymans <arthur@aheymans.xyz>2017-06-12 11:46:18 +0200
commit049347fee0e25c87c3f60b125ee5e03109429fb0 (patch)
tree0a3c69cef4722e22b485bd8002d8cd141b683b35 /src/mainboard/roda
parent9ed74b54b573d9f26ccd1ec382206c5c0c8048ff (diff)
downloadcoreboot-049347fee0e25c87c3f60b125ee5e03109429fb0.tar.xz
nb/intel/gm45: Add romstage timestamps
Change-Id: I558e6c63caf95ec5279ec5a866b54fb199116469 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19678 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/mainboard/roda')
-rw-r--r--src/mainboard/roda/rk9/romstage.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/mainboard/roda/rk9/romstage.c b/src/mainboard/roda/rk9/romstage.c
index 720f628ade..9a8e34b18b 100644
--- a/src/mainboard/roda/rk9/romstage.c
+++ b/src/mainboard/roda/rk9/romstage.c
@@ -32,6 +32,7 @@
#include <southbridge/intel/i82801ix/i82801ix.h>
#include <northbridge/intel/gm45/gm45.h>
#include <superio/smsc/lpc47n227/lpc47n227.h>
+#include <timestamp.h>
#define LPC_DEV PCI_DEV(0, 0x1f, 0)
#define SERIAL_DEV PNP_DEV(0x2e, LPC47N227_SP1)
@@ -124,6 +125,9 @@ void mainboard_romstage_entry(unsigned long bist)
int cbmem_initted;
u16 reg16;
+ timestamp_init(timestamp_get());
+ timestamp_add_now(TS_START_ROMSTAGE);
+
/* basic northbridge setup, including MMCONF BAR */
gm45_early_init();