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| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-11-09 14:19:04 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-12 18:22:57 +0000 |
| commit | fecf77770b8e68b9ef82021ca53c31db93736d93 (patch) | |
| tree | 001fba539061f4075699fc98e02b3153259477e9 /src/mainboard/roda | |
| parent | 675cb9152e6704383cf402c55758ddea2c7a1e05 (diff) | |
| download | coreboot-fecf77770b8e68b9ef82021ca53c31db93736d93.tar.xz | |
sb/intel/i82801gx: Add common LPC decode code
Generic LPC decode ranges can now be set from the devicetree.
Change-Id: I1065ec770ad3a743286859efa39dca09ccb733a1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36700
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/roda')
| -rw-r--r-- | src/mainboard/roda/rk886ex/devicetree.cb | 4 | ||||
| -rw-r--r-- | src/mainboard/roda/rk886ex/romstage.c | 21 |
2 files changed, 10 insertions, 15 deletions
diff --git a/src/mainboard/roda/rk886ex/devicetree.cb b/src/mainboard/roda/rk886ex/devicetree.cb index 0ceef6a2fd..5bce304335 100644 --- a/src/mainboard/roda/rk886ex/devicetree.cb +++ b/src/mainboard/roda/rk886ex/devicetree.cb @@ -62,6 +62,10 @@ chip northbridge/intel/i945 register "ide_enable_primary" = "0x1" register "ide_enable_secondary" = "0x0" + register "gen1_dec" = "0x001c02e1" # COM3, COM4 + register "gen2_dec" = "0x00fc0601" # ?? + register "gen3_dec" = "0x00040069" # EC decode ?? + device pci 1b.0 off end # High Definition Audio device pci 1c.0 on end # PCIe port 1 device pci 1c.1 off end # PCIe port 2 diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index e7724e4485..019ec1b733 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -30,26 +30,16 @@ #include <southbridge/intel/common/pmclib.h> #include "option_table.h" -static void ich7_enable_lpc(void) +/* Override the default lpc decode ranges */ +static void mb_lpc_decode(void) { int lpt_en = 0; if (read_option(lpt, 0) != 0) lpt_en = LPT_LPC_EN; /* enable LPT */ - /* Enable Serial IRQ */ - pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0); - /* decode range */ pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0007); - /* decode range */ - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN - | MC_LPC_EN | KBC_LPC_EN | GAMEH_LPC_EN | GAMEL_LPC_EN - | FDD_LPC_EN | lpt_en | COMB_LPC_EN | COMA_LPC_EN); - /* COM3 and COM4 decode? */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x1c02e1); - /* ??decode?? */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x00fc0601); - /* EC decode? */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN3_DEC, 0x00040069); + + pci_update_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, ~LPT_LPC_EN, lpt_en); } /* This box has two superios, so enabling serial becomes slightly excessive. @@ -177,7 +167,8 @@ void mainboard_romstage_entry(void) enable_lapic(); - ich7_enable_lpc(); + i82801gx_lpc_setup(); + mb_lpc_decode(); early_superio_config(); /* Set up the console */ |