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author | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2012-04-27 23:19:58 +0200 |
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committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2012-04-30 23:09:10 +0200 |
commit | 155e9b5533131f4b944ebb7e5714a871a1294dda (patch) | |
tree | 6d3cbc7a1442648560f94675a34268bbe1671e17 /src/mainboard/samsung/lumpy/acpi/superio.asl | |
parent | 6651da3bcd51ad6ea918c21564eb505b76c8c7aa (diff) | |
download | coreboot-155e9b5533131f4b944ebb7e5714a871a1294dda.tar.xz |
Add support for Sandybridge based Samsung ChromeBook
Change-Id: I8bf439bc903c1ec105016866753c7cb9ccfe5974
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/952
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/mainboard/samsung/lumpy/acpi/superio.asl')
-rw-r--r-- | src/mainboard/samsung/lumpy/acpi/superio.asl | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/src/mainboard/samsung/lumpy/acpi/superio.asl b/src/mainboard/samsung/lumpy/acpi/superio.asl new file mode 100644 index 0000000000..465fa54c91 --- /dev/null +++ b/src/mainboard/samsung/lumpy/acpi/superio.asl @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Values should match those defined in devicetree.cb */ + +#define SIO_ENABLE_SPM1 // pnp 2e.1: Enable ACPI PM1 Block +#define SIO_SPM1_IO0 0xb00 // pnp 2e.1: io 0x60 + +#undef SIO_ENABLE_SEC1 // pnp 2e.2: Disable EC 1 + +#undef SIO_ENABLE_SEC2 // pnp 2e.3: Disable EC 2 + +#undef SIO_ENABLE_SSP1 // pnp 2e.4: Disable UART + +#define SIO_ENABLE_SKBC // pnp 2e.7: Enable Keyboard + +#undef SIO_ENABLE_SEC0 // pnp 2e.8: Already exported as EC + +#define SIO_ENABLE_SMBX // pnp 2e.9: Enable Mailbox +#define SIO_SMBX_IO0 0xa00 // pnp 2e.9: io 0xa00 + +#include "../../../../superio/smsc/mec1308/acpi/superio.asl" |