Add support for Sandybridge based Samsung ChromeBook

Change-Id: I8bf439bc903c1ec105016866753c7cb9ccfe5974
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/952
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

8 files changed, 630 insertions, 0 deletions

diff --git a/src/mainboard/samsung/lumpy/acpi/chromeos.asl b/src/mainboard/samsung/lumpy/acpi/chromeos.asl
new file mode 100644
index 0000000000..fc7be2010e
--- /dev/null
+++ b/src/mainboard/samsung/lumpy/acpi/chromeos.asl
@@ -0,0 +1,114 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+Device (CRHW)
+{
+	Name(_HID, EISAID("GGL0001"))
+
+	Method(_STA, 0, Serialized)
+	{
+		Return (0xb)
+	}
+
+	Method(CHSW, 0, Serialized)
+	{
+		Name (WSHC, Package() { VBT3 })
+		Return (WSHC)
+	}
+
+	Method(FWID, 0, Serialized)
+	{
+		Name (DIW1, "")
+		ToString(VBT5, 63, DIW1)
+		Name (DIWF, Package() { DIW1 })
+		Return(DIWF)
+	}
+
+	Method(FRID, 0, Serialized)
+	{
+		Name (DIR1, "")
+		ToString(VBT6, 63, DIR1)
+		Name (DIRF, Package() { DIR1 })
+		Return (DIRF)
+	}
+
+	Method(HWID, 0, Serialized)
+	{
+		Name (DIW0, "")
+		ToString(VBT4, 255, DIW0)
+		Name (DIWH, Package() { DIW0 })
+		Return (DIWH)
+	}
+
+	Method(BINF, 0, Serialized)
+	{
+		Name (FNIB, Package() { VBT0, VBT1, VBT2, VBT7, VBT8 })
+		Return (FNIB)
+	}
+
+	Method(GPIO, 0, Serialized)
+	{
+		Name(OIPG, Package() {
+			Package() { 0x001, 0, 42, "CougarPoint" }, // recovery button
+			Package() { 0x002, 1, 17, "CougarPoint" }, // developer switch
+			Package() { 0x003, 1, 24, "CougarPoint" }, // firmware write protect
+		})
+		Return (OIPG)
+
+	}
+
+	Method(VBNV, 0, Serialized)
+	{
+		Name(VNBV, Package() {
+			// See src/vendorcode/google/chromeos/Kconfig
+			// for the definition of these:
+			CONFIG_VBNV_OFFSET,
+			CONFIG_VBNV_SIZE
+		})
+		Return(VNBV)
+	}
+
+	Method(VDAT, 0, Serialized)
+	{
+		Name(TAD0,"")
+		ToBuffer(CHVD, TAD0)
+		Name (TADV, Package() { TAD0 })
+		Return (TADV)
+	}
+
+	Method(FMAP, 0, Serialized)
+	{
+		Name(PAMF, Package() { VBT9 })
+		Return(PAMF)
+	}
+
+	Method(MECK, 0, Serialized)
+	{
+		Name(HASH, Package() { MEHH })
+		Return(HASH)
+	}
+
+	Method(MLST, 0, Serialized)
+	{
+		Name(TSLM, Package() { "CHSW", "FWID", "HWID", "FRID", "BINF",
+			   "GPIO", "VBNV", "VDAT", "FMAP", "MECK"
+		})
+		Return (TSLM)
+	}
+}
diff --git a/src/mainboard/samsung/lumpy/acpi/ec.asl b/src/mainboard/samsung/lumpy/acpi/ec.asl
new file mode 100644
index 0000000000..21602c2a35
--- /dev/null
+++ b/src/mainboard/samsung/lumpy/acpi/ec.asl
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* EC configuration */
+#define EC_GPE 23	// GPE23 -> Runtime SCI
+
+#include <ec/smsc/mec1308/acpi/ec.asl>
+
diff --git a/src/mainboard/samsung/lumpy/acpi/mainboard.asl b/src/mainboard/samsung/lumpy/acpi/mainboard.asl
new file mode 100644
index 0000000000..b1ab678310
--- /dev/null
+++ b/src/mainboard/samsung/lumpy/acpi/mainboard.asl
@@ -0,0 +1,79 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+Scope (\_SB) {
+	Device (LID0)
+	{
+		Name(_HID, EisaId("PNP0C0D"))
+		Method(_LID, 0)
+		{
+			Store (\_SB.PCI0.LPCB.EC0.LIDS, \LIDS)
+			Return (\LIDS)
+		}
+
+		// WAKE SCI# from EC is GPIO14
+		Name(_PRW, Package(){0x1e, 0x05})
+	}
+
+	Device (PWRB)
+	{
+		Name(_HID, EisaId("PNP0C0C"))
+	}
+
+	Device (TPAD)
+	{
+		// Report as a Sleep Button device so
+		// Linux will automatically enable for wake
+		Name(_HID, EisaId("PNP0C0E"))
+
+		// Trackpad Wake is GPIO11
+		Name(_PRW, Package(){0x1b, 0x03})
+
+		Name(_CRS, ResourceTemplate()
+		{
+			// PIRQF -> GSI21
+			Interrupt (ResourceConsumer, Edge, ActiveLow) {21}
+
+			// SMBUS Address 0x67
+			VendorShort (ADDR) {0x67}
+		})
+	}
+
+	Device (LITE)
+	{
+		// Generic ACPI Device Container
+		Name(_HID, EisaId("PNP0A05"))
+
+		Name(_CRS, ResourceTemplate()
+		{
+			// PIRQE -> GSI20
+			Interrupt (ResourceConsumer, Edge, ActiveLow) {20}
+
+			// SMBUS Address 0x44
+			VendorShort (ADDR) {0x44}
+		})
+	}
+}
+
+// Battery information
+Name (BATV, "SAMSUNG")
+Name (BATM, "LUMPY")
+Name (BATS, "BATTERY")
diff --git a/src/mainboard/samsung/lumpy/acpi/platform.asl b/src/mainboard/samsung/lumpy/acpi/platform.asl
new file mode 100644
index 0000000000..39a29e7168
--- /dev/null
+++ b/src/mainboard/samsung/lumpy/acpi/platform.asl
@@ -0,0 +1,117 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* The APM port can be used for generating software SMIs */
+
+OperationRegion (APMP, SystemIO, 0xb2, 2)
+Field (APMP, ByteAcc, NoLock, Preserve)
+{
+	APMC, 8,	// APM command
+	APMS, 8		// APM status
+}
+
+/* Port 80 POST */
+
+OperationRegion (POST, SystemIO, 0x80, 1)
+Field (POST, ByteAcc, Lock, Preserve)
+{
+	DBG0, 8
+}
+
+/* SMI I/O Trap */
+Method(TRAP, 1, Serialized)
+{
+	Store (Arg0, SMIF)	// SMI Function
+	Store (0, TRP0)		// Generate trap
+	Return (SMIF)		// Return value of SMI handler
+}
+
+/* The _PIC method is called by the OS to choose between interrupt
+ * routing via the i8259 interrupt controller or the APIC.
+ *
+ * _PIC is called with a parameter of 0 for i8259 configuration and
+ * with a parameter of 1 for Local Apic/IOAPIC configuration.
+ */
+
+Method(_PIC, 1)
+{
+	// Remember the OS' IRQ routing choice.
+	Store(Arg0, PICM)
+}
+
+/* The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0
+ */
+
+Method(_PTS,1)
+{
+	Store (Zero, GP35)  // Disable WLAN
+	Store (Zero, GP38)  // Disable WWAN
+
+	If (S33G) {
+		Store (Zero, GP43)  // Enable HSPA
+	} Else {
+		Store (One, GP43)   // Disable HSPA
+	}
+
+	If (LEqual (Arg0, 3)) {
+		// NVS has a flag to determine USB policy in S3
+		If (S3U0) {
+			Store (One, GP47)   // Enable USB0
+		} Else {
+			Store (Zero, GP47)  // Disable USB0
+		}
+
+		// NVS has a flag to determine USB policy in S3
+		If (S3U1) {
+			Store (One, GP56)   // Enable USB1
+		} Else {
+			Store (Zero, GP56)  // Disable USB1
+		}
+	}
+	If (LEqual (Arg0, 5)) {
+		// NVS has a flag to determine USB policy in S5
+		If (S5U0) {
+			Store (One, GP47)   // Enable USB0
+		} Else {
+			Store (Zero, GP47)  // Disable USB0
+		}
+
+		// NVS has a flag to determine USB policy in S5
+		If (S5U1) {
+			Store (One, GP56)   // Enable USB1
+		} Else {
+			Store (Zero, GP56)  // Disable USB1
+		}
+	}
+}
+
+/* The _WAK method is called on system wakeup */
+
+Method(_WAK,1)
+{
+	/* Update in case state changed while asleep */
+	Store (\_SB.PCI0.LPCB.EC0.ACEX, \PWRS)
+
+	/* Enable OS control of fan */
+	Store (One, \_SB.PCI0.LPCB.EC0.FCOS)
+
+	Return(Package(){0,0})
+}
+
diff --git a/src/mainboard/samsung/lumpy/acpi/sandybridge_pci_irqs.asl b/src/mainboard/samsung/lumpy/acpi/sandybridge_pci_irqs.asl
new file mode 100644
index 0000000000..179376e506
--- /dev/null
+++ b/src/mainboard/samsung/lumpy/acpi/sandybridge_pci_irqs.asl
@@ -0,0 +1,69 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* This is board specific information: IRQ routing for Sandybridge */
+
+// PCI Interrupt Routing
+Method(_PRT)
+{
+	If (PICM) {
+		Return (Package() {
+			// Onboard graphics (IGD)	0:2.0
+			Package() { 0x0002ffff, 0, 0, 16 },
+			// High Definition Audio	0:1b.0
+			Package() { 0x001bffff, 0, 0, 22 },
+			// PCIe Root Ports		0:1c.x
+			Package() { 0x001cffff, 0, 0, 17 },
+			Package() { 0x001cffff, 1, 0, 18 },
+			Package() { 0x001cffff, 2, 0, 19 },
+			Package() { 0x001cffff, 3, 0, 16 },
+			// EHCI	#1			0:1d.0
+			Package() { 0x001dffff, 0, 0, 19 },
+			// EHCI	#2			0:1a.0
+			Package() { 0x001affff, 0, 0, 17 },
+			// LPC devices			0:1f.0
+			Package() { 0x001fffff, 0, 0, 16 },
+			Package() { 0x001fffff, 1, 0, 22 },
+			Package() { 0x001fffff, 2, 0, 23 },
+			Package() { 0x001fffff, 3, 0, 17 },
+		})
+	} Else {
+		Return (Package() {
+			// Onboard graphics (IGD)	0:2.0
+			Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			// High Definition Audio	0:1b.0
+			Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
+			// PCIe Root Ports		0:1c.x
+			Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
+			Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKC, 0 },
+			Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 },
+			Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKE, 0 },
+			// EHCI	#1			0:1d.0
+			Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
+			// EHCI	#2			0:1a.0
+			Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
+			// LPC device			0:1f.0
+			Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKG, 0 },
+			Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKH, 0 },
+			Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKB, 0 },
+		})
+	}
+}
+
diff --git a/src/mainboard/samsung/lumpy/acpi/superio.asl b/src/mainboard/samsung/lumpy/acpi/superio.asl
new file mode 100644
index 0000000000..465fa54c91
--- /dev/null
+++ b/src/mainboard/samsung/lumpy/acpi/superio.asl
@@ -0,0 +1,38 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Values should match those defined in devicetree.cb */
+
+#define SIO_ENABLE_SPM1          // pnp 2e.1: Enable ACPI PM1 Block
+#define SIO_SPM1_IO0      0xb00  // pnp 2e.1: io 0x60
+
+#undef SIO_ENABLE_SEC1           // pnp 2e.2: Disable EC 1
+
+#undef SIO_ENABLE_SEC2           // pnp 2e.3: Disable EC 2
+
+#undef SIO_ENABLE_SSP1           // pnp 2e.4: Disable UART
+
+#define SIO_ENABLE_SKBC          // pnp 2e.7: Enable Keyboard
+
+#undef SIO_ENABLE_SEC0           // pnp 2e.8: Already exported as EC
+
+#define SIO_ENABLE_SMBX          // pnp 2e.9: Enable Mailbox
+#define SIO_SMBX_IO0      0xa00  // pnp 2e.9: io 0xa00
+
+#include "../../../../superio/smsc/mec1308/acpi/superio.asl"
diff --git a/src/mainboard/samsung/lumpy/acpi/thermal.asl b/src/mainboard/samsung/lumpy/acpi/thermal.asl
new file mode 100644
index 0000000000..b8fa750396
--- /dev/null
+++ b/src/mainboard/samsung/lumpy/acpi/thermal.asl
@@ -0,0 +1,146 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+// Thermal Zone
+
+Scope (\_TZ)
+{
+	ThermalZone (THRM)
+	{
+		Name (_TC1, 0x02)
+		Name (_TC2, 0x05)
+
+		// Ignore critical temps for the first few reads
+		// at boot to prevent unexpected shutdown
+		Name (IRDC, 4)
+		Name (CRDC, 0)
+
+		// Thermal zone polling frequency: 10 seconds
+		Name (_TZP, 100)
+
+		// Thermal sampling period for passive cooling: 2 seconds
+		Name (_TSP, 20)
+
+		// Convert from Degrees C to 1/10 Kelvin for ACPI
+		Method (CTOK, 1) {
+			// 10th of Degrees C
+			Multiply (Arg0, 10, Local0)
+
+			// Convert to Kelvin
+			Add (Local0, 2732, Local0)
+
+			Return (Local0)
+		}
+
+		// Threshold for OS to shutdown
+		Method (_CRT, 0, Serialized)
+		{
+			Return (CTOK (\TCRT))
+		}
+
+		// Threshold for passive cooling
+		Method (_PSV, 0, Serialized)
+		{
+			Return (CTOK (\TPSV))
+		}
+
+		// Processors used for passive cooling
+		Method (_PSL, 0, Serialized)
+		{
+			Return (\PPKG ())
+		}
+
+		Method (_TMP, 0, Serialized)
+		{
+			// Get CPU Temperature from the Embedded Controller
+			Store (\_SB.PCI0.LPCB.EC0.CPUT, Local0)
+
+			// Re-read from EC if the temperature is very high to
+			// avoid OS shutdown if we got a bad reading.
+			If (LGreaterEqual (Local0, \TCRT)) {
+				Store (\_SB.PCI0.LPCB.EC0.CPUT, Local0)
+				If (LGreaterEqual (Local0, \TCRT)) {
+					// Check if this is an early read
+					If (LLess (CRDC, IRDC)) {
+						Store (0, Local0)
+					}
+				}
+			}
+
+			// Keep track of first few reads by the OS
+			If (LLess (CRDC, IRDC)) {
+				Increment (CRDC)
+			}
+
+			// Invalid reading, ensure fan is spinning
+			If (LGreaterEqual (Local0, 0x80)) {
+				Return (CTOK (\F4ON))
+			}
+
+			Return (CTOK (Local0))
+		}
+
+		Method (_AC0) {
+			If (LLessEqual (\FLVL, 0)) {
+				Return (CTOK (\F0OF))
+			} Else {
+				Return (CTOK (\F0ON))
+			}
+		}
+
+		Method (_AC1) {
+			If (LLessEqual (\FLVL, 1)) {
+				Return (CTOK (\F1OF))
+			} Else {
+				Return (CTOK (\F1ON))
+			}
+		}
+
+		Method (_AC2) {
+			If (LLessEqual (\FLVL, 2)) {
+				Return (CTOK (\F2OF))
+			} Else {
+				Return (CTOK (\F2ON))
+			}
+		}
+
+		Method (_AC3) {
+			If (LLessEqual (\FLVL, 3)) {
+				Return (CTOK (\F3OF))
+			} Else {
+				Return (CTOK (\F3ON))
+			}
+		}
+
+		Method (_AC4) {
+			If (LLessEqual (\FLVL, 4)) {
+				Return (CTOK (\F4OF))
+			} Else {
+				Return (CTOK (\F4ON))
+			}
+		}
+
+		Name (_AL0, Package () { \_SB.PCI0.LPCB.EC0.FAN0 })
+		Name (_AL1, Package () { \_SB.PCI0.LPCB.EC0.FAN1 })
+		Name (_AL2, Package () { \_SB.PCI0.LPCB.EC0.FAN2 })
+		Name (_AL3, Package () { \_SB.PCI0.LPCB.EC0.FAN3 })
+		Name (_AL4, Package () { \_SB.PCI0.LPCB.EC0.FAN4 })
+	}
+}
+
diff --git a/src/mainboard/samsung/lumpy/acpi/video.asl b/src/mainboard/samsung/lumpy/acpi/video.asl
new file mode 100644
index 0000000000..3ececa912b
--- /dev/null
+++ b/src/mainboard/samsung/lumpy/acpi/video.asl
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+// Brightness write
+Method (BRTW, 1, Serialized)
+{
+	// TODO
+}
+
+// Hot Key Display Switch
+Method (HKDS, 1, Serialized)
+{
+	// TODO
+}
+
+// Lid Switch Display Switch
+Method (LSDS, 1, Serialized)
+{
+	// TODO
+}
+
+// Brightness Notification
+Method(BRTN,1,Serialized)
+{
+	// TODO (no displays defined yet)
+}
+