Add support for Sandybridge based Samsung ChromeBook

Change-Id: I8bf439bc903c1ec105016866753c7cb9ccfe5974 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/952 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
author: Stefan Reinauer <stefan.reinauer@coreboot.org> 2012-04-27 23:19:58 +0200
committer: Stefan Reinauer <stefan.reinauer@coreboot.org> 2012-04-30 23:09:10 +0200
commit: 155e9b5533131f4b944ebb7e5714a871a1294dda (patch)
tree: 6d3cbc7a1442648560f94675a34268bbe1671e17 /src/mainboard/samsung/lumpy
parent: 6651da3bcd51ad6ea918c21564eb505b76c8c7aa (diff)
download: coreboot-155e9b5533131f4b944ebb7e5714a871a1294dda.tar.xz
27 files changed, 3208 insertions, 0 deletions
diff --git a/src/mainboard/samsung/lumpy/Kconfig b/src/mainboard/samsung/lumpy/Kconfig
new file mode 100644
index 0000000000..200edac3a5
--- /dev/null
+++ b/src/mainboard/samsung/lumpy/Kconfig
@@ -0,0 +1,59 @@
+if BOARD_SAMSUNG_LUMPY
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select ARCH_X86
+	select BOARD_HAS_FADT
+	select BOARD_ROMSIZE_KB_8192
+	select CHROMEOS
+	select CPU_INTEL_SOCKET_RPGA989
+	select EC_SMSC_MEC1308
+	select EXTERNAL_MRC_BLOB
+	select GFXUMA
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select HAVE_MAINBOARD_RESOURCES
+	select HAVE_OPTION_TABLE
+	select HAVE_SMI_HANDLER
+	select MMCONF_SUPPORT
+	select NORTHBRIDGE_INTEL_SANDYBRIDGE
+	select SOUTHBRIDGE_INTEL_BD82X6X
+	select SUPERIO_SMSC_MEC1308
+
+config MAINBOARD_DIR
+	string
+	default samsung/lumpy
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "Lumpy"
+
+config MMCONF_BASE_ADDRESS
+	hex
+	default 0xf0000000
+
+config IRQ_SLOT_COUNT
+	int
+	default 18
+
+config MAX_CPUS
+	int
+	default 8
+
+config VGA_BIOS_FILE
+	string
+	default "pci8086,0106.rom"
+
+config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+	hex
+	default 0x1ae0
+
+config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+	hex
+	default 0xc000
+
+config MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+	bool
+	default n
+
+endif # BOARD_SAMSUNG_LUMPY
diff --git a/src/mainboard/samsung/lumpy/Makefile.inc b/src/mainboard/samsung/lumpy/Makefile.inc
new file mode 100644
index 0000000000..f25aaa5854
--- /dev/null
+++ b/src/mainboard/samsung/lumpy/Makefile.inc
@@ -0,0 +1,35 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+ramstage-y += ec.c
+
+romstage-$(CONFIG_CHROMEOS) += chromeos.c
+ramstage-$(CONFIG_CHROMEOS) += chromeos.c
+
+smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c
+SPD_BIN = $(obj)/spd.bin
+
+# Include spd rom data
+$(SPD_BIN):
+	xxd -rg1 $(src)/mainboard/samsung/lumpy/spd.hex >| $@
+
+cbfs-files-y += spd.bin
+spd.bin-file := $(SPD_BIN)
+spd.bin-type := 0xab
+spd.bin-position := 0xfffdc000
diff --git a/src/mainboard/samsung/lumpy/acpi/chromeos.asl b/src/mainboard/samsung/lumpy/acpi/chromeos.asl
new file mode 100644
index 0000000000..fc7be2010e
--- /dev/null
+++ b/src/mainboard/samsung/lumpy/acpi/chromeos.asl
@@ -0,0 +1,114 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+Device (CRHW)
+{
+	Name(_HID, EISAID("GGL0001"))
+
+	Method(_STA, 0, Serialized)
+	{
+		Return (0xb)
+	}
+
+	Method(CHSW, 0, Serialized)
+	{
+		Name (WSHC, Package() { VBT3 })
+		Return (WSHC)
+	}
+
+	Method(FWID, 0, Serialized)
+	{
+		Name (DIW1, "")
+		ToString(VBT5, 63, DIW1)
+		Name (DIWF, Package() { DIW1 })
+		Return(DIWF)
+	}
+
+	Method(FRID, 0, Serialized)
+	{
+		Name (DIR1, "")
+		ToString(VBT6, 63, DIR1)
+		Name (DIRF, Package() { DIR1 })
+		Return (DIRF)
+	}
+
+	Method(HWID, 0, Serialized)
+	{
+		Name (DIW0, "")
+		ToString(VBT4, 255, DIW0)
+		Name (DIWH, Package() { DIW0 })
+		Return (DIWH)
+	}
+
+	Method(BINF, 0, Serialized)
+	{
+		Name (FNIB, Package() { VBT0, VBT1, VBT2, VBT7, VBT8 })
+		Return (FNIB)
+	}
+
+	Method(GPIO, 0, Serialized)
+	{
+		Name(OIPG, Package() {
+			Package() { 0x001, 0, 42, "CougarPoint" }, // recovery button
+			Package() { 0x002, 1, 17, "CougarPoint" }, // developer switch
+			Package() { 0x003, 1, 24, "CougarPoint" }, // firmware write protect
+		})
+		Return (OIPG)
+
+	}
+
+	Method(VBNV, 0, Serialized)
+	{
+		Name(VNBV, Package() {
+			// See src/vendorcode/google/chromeos/Kconfig
+			// for the definition of these:
+			CONFIG_VBNV_OFFSET,
+			CONFIG_VBNV_SIZE
+		})
+		Return(VNBV)
+	}
+
+	Method(VDAT, 0, Serialized)
+	{
+		Name(TAD0,"")
+		ToBuffer(CHVD, TAD0)
+		Name (TADV, Package() { TAD0 })
+		Return (TADV)
+	}
+
+	Method(FMAP, 0, Serialized)
+	{
+		Name(PAMF, Package() { VBT9 })
+		Return(PAMF)
+	}
+
+	Method(MECK, 0, Serialized)
+	{
+		Name(HASH, Package() { MEHH })
+		Return(HASH)
+	}
+
+	Method(MLST, 0, Serialized)
+	{
+		Name(TSLM, Package() { "CHSW", "FWID", "HWID", "FRID", "BINF",
+			   "GPIO", "VBNV", "VDAT", "FMAP", "MECK"
+		})
+		Return (TSLM)
+	}
+}
diff --git a/src/mainboard/samsung/lumpy/acpi/ec.asl b/src/mainboard/samsung/lumpy/acpi/ec.asl
new file mode 100644
index 0000000000..21602c2a35
--- /dev/null
+++ b/src/mainboard/samsung/lumpy/acpi/ec.asl
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* EC configuration */
+#define EC_GPE 23	// GPE23 -> Runtime SCI
+
+#include <ec/smsc/mec1308/acpi/ec.asl>
+
diff --git a/src/mainboard/samsung/lumpy/acpi/mainboard.asl b/src/mainboard/samsung/lumpy/acpi/mainboard.asl
new file mode 100644
index 0000000000..b1ab678310
--- /dev/null
+++ b/src/mainboard/samsung/lumpy/acpi/mainboard.asl
@@ -0,0 +1,79 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+Scope (\_SB) {
+	Device (LID0)
+	{
+		Name(_HID, EisaId("PNP0C0D"))
+		Method(_LID, 0)
+		{
+			Store (\_SB.PCI0.LPCB.EC0.LIDS, \LIDS)
+			Return (\LIDS)
+		}
+
+		// WAKE SCI# from EC is GPIO14
+		Name(_PRW, Package(){0x1e, 0x05})
+	}
+
+	Device (PWRB)
+	{
+		Name(_HID, EisaId("PNP0C0C"))
+	}
+
+	Device (TPAD)
+	{
+		// Report as a Sleep Button device so
+		// Linux will automatically enable for wake
+		Name(_HID, EisaId("PNP0C0E"))
+
+		// Trackpad Wake is GPIO11
+		Name(_PRW, Package(){0x1b, 0x03})
+
+		Name(_CRS, ResourceTemplate()
+		{
+			// PIRQF -> GSI21
+			Interrupt (ResourceConsumer, Edge, ActiveLow) {21}
+
+			// SMBUS Address 0x67
+			VendorShort (ADDR) {0x67}
+		})
+	}
+
+	Device (LITE)
+	{
+		// Generic ACPI Device Container
+		Name(_HID, EisaId("PNP0A05"))
+
+		Name(_CRS, ResourceTemplate()
+		{
+			// PIRQE -> GSI20
+			Interrupt (ResourceConsumer, Edge, ActiveLow) {20}
+
+			// SMBUS Address 0x44
+			VendorShort (ADDR) {0x44}
+		})
+	}
+}
+
+// Battery information
+Name (BATV, "SAMSUNG")
+Name (BATM, "LUMPY")
+Name (BATS, "BATTERY")
diff --git a/src/mainboard/samsung/lumpy/acpi/platform.asl b/src/mainboard/samsung/lumpy/acpi/platform.asl
new file mode 100644
index 0000000000..39a29e7168
--- /dev/null
+++ b/src/mainboard/samsung/lumpy/acpi/platform.asl
@@ -0,0 +1,117 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* The APM port can be used for generating software SMIs */
+
+OperationRegion (APMP, SystemIO, 0xb2, 2)
+Field (APMP, ByteAcc, NoLock, Preserve)
+{
+	APMC, 8,	// APM command
+	APMS, 8		// APM status
+}
+
+/* Port 80 POST */
+
+OperationRegion (POST, SystemIO, 0x80, 1)
+Field (POST, ByteAcc, Lock, Preserve)
+{
+	DBG0, 8
+}
+
+/* SMI I/O Trap */
+Method(TRAP, 1, Serialized)
+{
+	Store (Arg0, SMIF)	// SMI Function
+	Store (0, TRP0)		// Generate trap
+	Return (SMIF)		// Return value of SMI handler
+}
+
+/* The _PIC method is called by the OS to choose between interrupt
+ * routing via the i8259 interrupt controller or the APIC.
+ *
+ * _PIC is called with a parameter of 0 for i8259 configuration and
+ * with a parameter of 1 for Local Apic/IOAPIC configuration.
+ */
+
+Method(_PIC, 1)
+{
+	// Remember the OS' IRQ routing choice.
+	Store(Arg0, PICM)
+}
+
+/* The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0
+ */
+
+Method(_PTS,1)
+{
+	Store (Zero, GP35)  // Disable WLAN
+	Store (Zero, GP38)  // Disable WWAN
+
+	If (S33G) {
+		Store (Zero, GP43)  // Enable HSPA
+	} Else {
+		Store (One, GP43)   // Disable HSPA
+	}
+
+	If (LEqual (Arg0, 3)) {
+		// NVS has a flag to determine USB policy in S3
+		If (S3U0) {
+			Store (One, GP47)   // Enable USB0
+		} Else {
+			Store (Zero, GP47)  // Disable USB0
+		}
+
+		// NVS has a flag to determine USB policy in S3
+		If (S3U1) {
+			Store (One, GP56)   // Enable USB1
+		} Else {
+			Store (Zero, GP56)  // Disable USB1
+		}
+	}
+	If (LEqual (Arg0, 5)) {
+		// NVS has a flag to determine USB policy in S5
+		If (S5U0) {
+			Store (One, GP47)   // Enable USB0
+		} Else {
+			Store (Zero, GP47)  // Disable USB0
+		}
+
+		// NVS has a flag to determine USB policy in S5
+		If (S5U1) {
+			Store (One, GP56)   // Enable USB1
+		} Else {
+			Store (Zero, GP56)  // Disable USB1
+		}
+	}
+}
+
+/* The _WAK method is called on system wakeup */
+
+Method(_WAK,1)
+{
+	/* Update in case state changed while asleep */
+	Store (\_SB.PCI0.LPCB.EC0.ACEX, \PWRS)
+
+	/* Enable OS control of fan */
+	Store (One, \_SB.PCI0.LPCB.EC0.FCOS)
+
+	Return(Package(){0,0})
+}
+
diff --git a/src/mainboard/samsung/lumpy/acpi/sandybridge_pci_irqs.asl b/src/mainboard/samsung/lumpy/acpi/sandybridge_pci_irqs.asl
new file mode 100644
index 0000000000..179376e506
--- /dev/null
+++ b/src/mainboard/samsung/lumpy/acpi/sandybridge_pci_irqs.asl
@@ -0,0 +1,69 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* This is board specific information: IRQ routing for Sandybridge */
+
+// PCI Interrupt Routing
+Method(_PRT)
+{
+	If (PICM) {
+		Return (Package() {
+			// Onboard graphics (IGD)	0:2.0
+			Package() { 0x0002ffff, 0, 0, 16 },
+			// High Definition Audio	0:1b.0
+			Package() { 0x001bffff, 0, 0, 22 },
+			// PCIe Root Ports		0:1c.x
+			Package() { 0x001cffff, 0, 0, 17 },
+			Package() { 0x001cffff, 1, 0, 18 },
+			Package() { 0x001cffff, 2, 0, 19 },
+			Package() { 0x001cffff, 3, 0, 16 },
+			// EHCI	#1			0:1d.0
+			Package() { 0x001dffff, 0, 0, 19 },
+			// EHCI	#2			0:1a.0
+			Package() { 0x001affff, 0, 0, 17 },
+			// LPC devices			0:1f.0
+			Package() { 0x001fffff, 0, 0, 16 },
+			Package() { 0x001fffff, 1, 0, 22 },
+			Package() { 0x001fffff, 2, 0, 23 },
+			Package() { 0x001fffff, 3, 0, 17 },
+		})
+	} Else {
+		Return (Package() {
+			// Onboard graphics (IGD)	0:2.0
+			Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			// High Definition Audio	0:1b.0
+			Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
+			// PCIe Root Ports		0:1c.x
+			Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
+			Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKC, 0 },
+			Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 },
+			Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKE, 0 },
+			// EHCI	#1			0:1d.0
+			Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
+			// EHCI	#2			0:1a.0
+			Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
+			// LPC device			0:1f.0
+			Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKG, 0 },
+			Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKH, 0 },
+			Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKB, 0 },
+		})
+	}
+}
+
diff --git a/src/mainboard/samsung/lumpy/acpi/superio.asl b/src/mainboard/samsung/lumpy/acpi/superio.asl
new file mode 100644
index 0000000000..465fa54c91
--- /dev/null
+++ b/src/mainboard/samsung/lumpy/acpi/superio.asl
@@ -0,0 +1,38 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Values should match those defined in devicetree.cb */
+
+#define SIO_ENABLE_SPM1          // pnp 2e.1: Enable ACPI PM1 Block
+#define SIO_SPM1_IO0      0xb00  // pnp 2e.1: io 0x60
+
+#undef SIO_ENABLE_SEC1           // pnp 2e.2: Disable EC 1
+
+#undef SIO_ENABLE_SEC2           // pnp 2e.3: Disable EC 2
+
+#undef SIO_ENABLE_SSP1           // pnp 2e.4: Disable UART
+
+#define SIO_ENABLE_SKBC          // pnp 2e.7: Enable Keyboard
+
+#undef SIO_ENABLE_SEC0           // pnp 2e.8: Already exported as EC
+
+#define SIO_ENABLE_SMBX          // pnp 2e.9: Enable Mailbox
+#define SIO_SMBX_IO0      0xa00  // pnp 2e.9: io 0xa00
+
+#include "../../../../superio/smsc/mec1308/acpi/superio.asl"
diff --git a/src/mainboard/samsung/lumpy/acpi/thermal.asl b/src/mainboard/samsung/lumpy/acpi/thermal.asl
new file mode 100644
index 0000000000..b8fa750396
--- /dev/null
+++ b/src/mainboard/samsung/lumpy/acpi/thermal.asl
@@ -0,0 +1,146 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+// Thermal Zone
+
+Scope (\_TZ)
+{
+	ThermalZone (THRM)
+	{
+		Name (_TC1, 0x02)
+		Name (_TC2, 0x05)
+
+		// Ignore critical temps for the first few reads
+		// at boot to prevent unexpected shutdown
+		Name (IRDC, 4)
+		Name (CRDC, 0)
+
+		// Thermal zone polling frequency: 10 seconds
+		Name (_TZP, 100)
+
+		// Thermal sampling period for passive cooling: 2 seconds
+		Name (_TSP, 20)
+
+		// Convert from Degrees C to 1/10 Kelvin for ACPI
+		Method (CTOK, 1) {
+			// 10th of Degrees C
+			Multiply (Arg0, 10, Local0)
+
+			// Convert to Kelvin
+			Add (Local0, 2732, Local0)
+
+			Return (Local0)
+		}
+
+		// Threshold for OS to shutdown
+		Method (_CRT, 0, Serialized)
+		{
+			Return (CTOK (\TCRT))
+		}
+
+		// Threshold for passive cooling
+		Method (_PSV, 0, Serialized)
+		{
+			Return (CTOK (\TPSV))
+		}
+
+		// Processors used for passive cooling
+		Method (_PSL, 0, Serialized)
+		{
+			Return (\PPKG ())
+		}
+
+		Method (_TMP, 0, Serialized)
+		{
+			// Get CPU Temperature from the Embedded Controller
+			Store (\_SB.PCI0.LPCB.EC0.CPUT, Local0)
+
+			// Re-read from EC if the temperature is very high to
+			// avoid OS shutdown if we got a bad reading.
+			If (LGreaterEqual (Local0, \TCRT)) {
+				Store (\_SB.PCI0.LPCB.EC0.CPUT, Local0)
+				If (LGreaterEqual (Local0, \TCRT)) {
+					// Check if this is an early read
+					If (LLess (CRDC, IRDC)) {
+						Store (0, Local0)
+					}
+				}
+			}
+
+			// Keep track of first few reads by the OS
+			If (LLess (CRDC, IRDC)) {
+				Increment (CRDC)
+			}
+
+			// Invalid reading, ensure fan is spinning
+			If (LGreaterEqual (Local0, 0x80)) {
+				Return (CTOK (\F4ON))
+			}
+
+			Return (CTOK (Local0))
+		}
+
+		Method (_AC0) {
+			If (LLessEqual (\FLVL, 0)) {
+				Return (CTOK (\F0OF))
+			} Else {
+				Return (CTOK (\F0ON))
+			}
+		}
+
+		Method (_AC1) {
+			If (LLessEqual (\FLVL, 1)) {
+				Return (CTOK (\F1OF))
+			} Else {
+				Return (CTOK (\F1ON))
+			}
+		}
+
+		Method (_AC2) {
+			If (LLessEqual (\FLVL, 2)) {
+				Return (CTOK (\F2OF))
+			} Else {
+				Return (CTOK (\F2ON))
+			}
+		}
+
+		Method (_AC3) {
+			If (LLessEqual (\FLVL, 3)) {
+				Return (CTOK (\F3OF))
+			} Else {
+				Return (CTOK (\F3ON))
+			}
+		}
+
+		Method (_AC4) {
+			If (LLessEqual (\FLVL, 4)) {
+				Return (CTOK (\F4OF))
+			} Else {
+				Return (CTOK (\F4ON))
+			}
+		}
+
+		Name (_AL0, Package () { \_SB.PCI0.LPCB.EC0.FAN0 })
+		Name (_AL1, Package () { \_SB.PCI0.LPCB.EC0.FAN1 })
+		Name (_AL2, Package () { \_SB.PCI0.LPCB.EC0.FAN2 })
+		Name (_AL3, Package () { \_SB.PCI0.LPCB.EC0.FAN3 })
+		Name (_AL4, Package () { \_SB.PCI0.LPCB.EC0.FAN4 })
+	}
+}
+
diff --git a/src/mainboard/samsung/lumpy/acpi/video.asl b/src/mainboard/samsung/lumpy/acpi/video.asl
new file mode 100644
index 0000000000..3ececa912b
--- /dev/null
+++ b/src/mainboard/samsung/lumpy/acpi/video.asl
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+// Brightness write
+Method (BRTW, 1, Serialized)
+{
+	// TODO
+}
+
+// Hot Key Display Switch
+Method (HKDS, 1, Serialized)
+{
+	// TODO
+}
+
+// Lid Switch Display Switch
+Method (LSDS, 1, Serialized)
+{
+	// TODO
+}
+
+// Brightness Notification
+Method(BRTN,1,Serialized)
+{
+	// TODO (no displays defined yet)
+}
+
diff --git a/src/mainboard/samsung/lumpy/acpi_tables.c b/src/mainboard/samsung/lumpy/acpi_tables.c
new file mode 100644
index 0000000000..a9eeb74664
--- /dev/null
+++ b/src/mainboard/samsung/lumpy/acpi_tables.c
@@ -0,0 +1,323 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <string.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <arch/ioapic.h>
+#include <arch/acpigen.h>
+#include <arch/smp/mpspec.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <cpu/x86/msr.h>
+#include <ec/acpi/ec.h>
+#include <vendorcode/google/chromeos/gnvs.h>
+
+extern const unsigned char AmlCode[];
+#if CONFIG_HAVE_ACPI_SLIC
+unsigned long acpi_create_slic(unsigned long current);
+#endif
+
+#include "southbridge/intel/bd82x6x/nvs.h"
+#include "thermal.h"
+
+static global_nvs_t *gnvs_;
+
+static void acpi_update_thermal_table(global_nvs_t *gnvs)
+{
+	gnvs->f4of = FAN4_THRESHOLD_OFF;
+	gnvs->f4on = FAN4_THRESHOLD_ON;
+
+	gnvs->f3of = FAN3_THRESHOLD_OFF;
+	gnvs->f3on = FAN3_THRESHOLD_ON;
+
+	gnvs->f2of = FAN2_THRESHOLD_OFF;
+	gnvs->f2on = FAN2_THRESHOLD_ON;
+
+	gnvs->f1of = FAN1_THRESHOLD_OFF;
+	gnvs->f1on = FAN1_THRESHOLD_ON;
+
+	gnvs->f0of = FAN0_THRESHOLD_OFF;
+	gnvs->f0on = FAN0_THRESHOLD_ON;
+
+	gnvs->tcrt = CRITICAL_TEMPERATURE;
+	gnvs->tpsv = PASSIVE_TEMPERATURE;
+	gnvs->tmax = MAX_TEMPERATURE;
+	gnvs->flvl = 5;
+}
+
+static void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+	gnvs_ = gnvs;
+	memset((void *)gnvs, 0, sizeof(*gnvs));
+	gnvs->apic = 1;
+	gnvs->mpen = 1; /* Enable Multi Processing */
+	gnvs->pcnt = dev_count_cpu();
+
+	/*
+	 * Disable 3G in suspend by default.
+	 * Provide option to enable for http://crosbug.com/p/7925
+	 */
+	gnvs->s33g = 0;
+
+	/* Disable USB ports in S3 by default */
+	gnvs->s3u0 = 0;
+	gnvs->s3u1 = 0;
+
+	/* Disable USB ports in S5 by default */
+	gnvs->s5u0 = 0;
+	gnvs->s5u1 = 0;
+
+	/* CBMEM TOC */
+	gnvs->cmem = (u32)get_cbmem_toc();
+
+	/* IGD Displays */
+	gnvs->ndid = 3;
+	gnvs->did[0] = 0x80000100;
+	gnvs->did[1] = 0x80000240;
+	gnvs->did[2] = 0x80000410;
+	gnvs->did[3] = 0x80000410;
+	gnvs->did[4] = 0x00000005;
+
+	// TODO(reinauer) this could move elsewhere?
+	chromeos_init_vboot(&(gnvs->chromeos));
+
+	acpi_update_thermal_table(gnvs);
+
+	gnvs->chromeos.vbt2 = ec_read(0xcb) ? ACTIVE_ECFW_RW : ACTIVE_ECFW_RO;
+}
+
+static void acpi_create_intel_hpet(acpi_hpet_t * hpet)
+{
+#define HPET_ADDR  0xfed00000ULL
+	acpi_header_t *header = &(hpet->header);
+	acpi_addr_t *addr = &(hpet->addr);
+
+	memset((void *) hpet, 0, sizeof(acpi_hpet_t));
+
+	/* fill out header fields */
+	memcpy(header->signature, "HPET", 4);
+	memcpy(header->oem_id, OEM_ID, 6);
+	memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
+	memcpy(header->asl_compiler_id, ASLC, 4);
+
+	header->length = sizeof(acpi_hpet_t);
+	header->revision = 1;
+
+	/* fill out HPET address */
+	addr->space_id = 0;	/* Memory */
+	addr->bit_width = 64;
+	addr->bit_offset = 0;
+	addr->addrl = HPET_ADDR & 0xffffffff;
+	addr->addrh = HPET_ADDR >> 32;
+
+	hpet->id = 0x8086a201;	/* Intel */
+	hpet->number = 0x00;
+	hpet->min_tick = 0x0080;
+
+	header->checksum =
+	    acpi_checksum((void *) hpet, sizeof(acpi_hpet_t));
+}
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+	/* Local APICs */
+	current = acpi_create_madt_lapics(current);
+
+	/* IOAPIC */
+	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+				2, IO_APIC_ADDR, 0);
+
+	/* INT_SRC_OVR */
+	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+		 current, 0, 0, 2, 0);
+	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+		 current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH);
+
+	return current;
+}
+
+unsigned long acpi_fill_ssdt_generator(unsigned long current,
+					const char *oem_table_id)
+{
+	generate_cpu_entries();
+	return (unsigned long) (acpigen_get_current());
+}
+
+unsigned long acpi_fill_slit(unsigned long current)
+{
+	// Not implemented
+	return current;
+}
+
+unsigned long acpi_fill_srat(unsigned long current)
+{
+	/* No NUMA, no SRAT */
+	return current;
+}
+
+void smm_setup_structures(void *gnvs, void *tcg, void *smi1);
+
+#define ALIGN_CURRENT current = ((current + 0x0f) & -0x10)
+unsigned long write_acpi_tables(unsigned long start)
+{
+	unsigned long current;
+	int i;
+	acpi_rsdp_t *rsdp;
+	acpi_rsdt_t *rsdt;
+	acpi_xsdt_t *xsdt;
+	acpi_hpet_t *hpet;
+	acpi_madt_t *madt;
+	acpi_mcfg_t *mcfg;
+	acpi_fadt_t *fadt;
+	acpi_facs_t *facs;
+#if CONFIG_HAVE_ACPI_SLIC
+	acpi_header_t *slic;
+#endif
+	acpi_header_t *ssdt;
+	acpi_header_t *dsdt;
+
+	current = start;
+
+	/* Align ACPI tables to 16byte */
+	ALIGN_CURRENT;
+
+	printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start);
+
+	/* We need at least an RSDP and an RSDT Table */
+	rsdp = (acpi_rsdp_t *) current;
+	current += sizeof(acpi_rsdp_t);
+	ALIGN_CURRENT;
+	rsdt = (acpi_rsdt_t *) current;
+	current += sizeof(acpi_rsdt_t);
+	ALIGN_CURRENT;
+	xsdt = (acpi_xsdt_t *) current;
+	current += sizeof(acpi_xsdt_t);
+	ALIGN_CURRENT;
+
+	/* clear all table memory */
+	memset((void *) start, 0, current - start);
+
+	acpi_write_rsdp(rsdp, rsdt, xsdt);
+	acpi_write_rsdt(rsdt);
+	acpi_write_xsdt(xsdt);
+
+	printk(BIOS_DEBUG, "ACPI:    * FACS\n");
+	facs = (acpi_facs_t *) current;
+	current += sizeof(acpi_facs_t);
+	ALIGN_CURRENT;
+	acpi_create_facs(facs);
+
+	printk(BIOS_DEBUG, "ACPI:    * DSDT\n");
+	dsdt = (acpi_header_t *) current;
+	memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
+	current += dsdt->length;
+	memcpy(dsdt, &AmlCode, dsdt->length);
+
+	ALIGN_CURRENT;
+
+	printk(BIOS_DEBUG, "ACPI:    * FADT\n");
+	fadt = (acpi_fadt_t *) current;
+	current += sizeof(acpi_fadt_t);
+	ALIGN_CURRENT;
+
+	acpi_create_fadt(fadt, facs, dsdt);
+	acpi_add_table(rsdp, fadt);
+
+	/*
+	 * We explicitly add these tables later on:
+	 */
+	printk(BIOS_DEBUG, "ACPI:    * HPET\n");
+
+	hpet = (acpi_hpet_t *) current;
+	current += sizeof(acpi_hpet_t);
+	ALIGN_CURRENT;
+	acpi_create_intel_hpet(hpet);
+	acpi_add_table(rsdp, hpet);
+
+	/* If we want to use HPET Timers Linux wants an MADT */
+	printk(BIOS_DEBUG, "ACPI:    * MADT\n");
+
+	madt = (acpi_madt_t *) current;
+	acpi_create_madt(madt);
+	current += madt->header.length;
+	ALIGN_CURRENT;
+	acpi_add_table(rsdp, madt);
+
+	printk(BIOS_DEBUG, "ACPI:    * MCFG\n");
+	mcfg = (acpi_mcfg_t *) current;
+	acpi_create_mcfg(mcfg);
+	current += mcfg->header.length;
+	ALIGN_CURRENT;
+	acpi_add_table(rsdp, mcfg);
+
+	/* Pack GNVS into the ACPI table area */
+	for (i=0; i < dsdt->length; i++) {
+		if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) {
+			printk(BIOS_DEBUG, "ACPI: Patching up global NVS in "
+			     "DSDT at offset 0x%04x -> 0x%08lx\n", i, current);
+			*(u32*)(((u32)dsdt) + i) = current; // 0x92 bytes
+			break;
+		}
+	}
+
+	/* And fill it */
+	acpi_create_gnvs((global_nvs_t *)current);
+
+	/* And tell SMI about it */
+	smm_setup_structures((void *)current, NULL, NULL);
+
+	current += sizeof(global_nvs_t);
+	ALIGN_CURRENT;
+
+	/* We patched up the DSDT, so we need to recalculate the checksum */
+	dsdt->checksum = 0;
+	dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length);
+
+	printk(BIOS_DEBUG, "ACPI:     * DSDT @ %p Length %x\n", dsdt,
+		     dsdt->length);
+
+#if CONFIG_HAVE_ACPI_SLIC
+	printk(BIOS_DEBUG, "ACPI:     * SLIC\n");
+	slic = (acpi_header_t *)current;
+	current += acpi_create_slic(current);
+	ALIGN_CURRENT;
+	acpi_add_table(rsdp, slic);
+#endif
+
+	printk(BIOS_DEBUG, "ACPI:     * SSDT\n");
+	ssdt = (acpi_header_t *)current;
+	acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR);
+	current += ssdt->length;
+	acpi_add_table(rsdp, ssdt);
+	ALIGN_CURRENT;
+
+	printk(BIOS_DEBUG, "current = %lx\n", current);
+	printk(BIOS_INFO, "ACPI: done.\n");
+	return current;
+}
+
+void acpi_get_vdat_info(void **vdat_addr, uint32_t *vdat_size)
+{
+	*vdat_addr = &gnvs_->chromeos.vdat;
+	*vdat_size = sizeof(gnvs_->chromeos.vdat);
+}
diff --git a/src/mainboard/samsung/lumpy/chip.h b/src/mainboard/samsung/lumpy/chip.h
new file mode 100644
index 0000000000..831a9737ea
--- /dev/null
+++ b/src/mainboard/samsung/lumpy/chip.h
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+extern struct chip_operations mainboard_ops;
+struct mainboard_config {};
diff --git a/src/mainboard/samsung/lumpy/chromeos.c b/src/mainboard/samsung/lumpy/chromeos.c
new file mode 100644
index 0000000000..6d93470b74
--- /dev/null
+++ b/src/mainboard/samsung/lumpy/chromeos.c
@@ -0,0 +1,135 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <string.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+#include <arch/io.h>
+#ifdef __PRE_RAM__
+#include <arch/romcc_io.h>
+#else
+#include <device/device.h>
+#include <device/pci.h>
+#endif
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+
+#define GPIO_SPI_WP	24
+#define GPIO_REC_MODE	42
+#define GPIO_DEV_MODE	17
+
+#define FLAG_SPI_WP	0
+#define FLAG_REC_MODE	1
+#define FLAG_DEV_MODE	2
+
+#ifndef __PRE_RAM__
+#include <boot/coreboot_tables.h>
+#include <arch/coreboot_tables.h>
+#include "ec.h"
+#include <ec/smsc/mec1308/ec.h>
+
+#define GPIO_COUNT	5
+#define ACTIVE_LOW	0
+#define ACTIVE_HIGH	1
+
+void fill_lb_gpios(struct lb_gpios *gpios)
+{
+	device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
+	u16 gen_pmcon_1 = pci_read_config32(dev, GEN_PMCON_1);
+	u8  lid = ec_read(0x83);
+
+	gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio));
+	gpios->count = GPIO_COUNT;
+
+	/* Write Protect: GPIO24 = KBC3_SPI_WP# */
+	gpios->gpios[0].port = GPIO_SPI_WP;
+	gpios->gpios[0].polarity = ACTIVE_HIGH;
+	gpios->gpios[0].value =
+		(pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x1f, 2)),
+						 SATA_SP) >> FLAG_SPI_WP) & 1;
+	strncpy((char *)gpios->gpios[0].name,"write protect",
+							GPIO_MAX_NAME_LENGTH);
+
+	/* Recovery: GPIO42 = CHP3_REC_MODE# */
+	gpios->gpios[1].port = GPIO_REC_MODE;
+	gpios->gpios[1].polarity = ACTIVE_LOW;
+	gpios->gpios[1].value = !get_recovery_mode_switch();
+	strncpy((char *)gpios->gpios[1].name,"recovery", GPIO_MAX_NAME_LENGTH);
+
+	/* Developer: GPIO17 = KBC3_DVP_MODE */
+	gpios->gpios[2].port = GPIO_DEV_MODE;
+	gpios->gpios[2].polarity = ACTIVE_HIGH;
+	gpios->gpios[2].value = get_developer_mode_switch();
+	strncpy((char *)gpios->gpios[2].name,"developer", GPIO_MAX_NAME_LENGTH);
+
+	gpios->gpios[3].port = 100;
+	gpios->gpios[3].polarity = ACTIVE_HIGH;
+	gpios->gpios[3].value = lid & 1;
+	strncpy((char *)gpios->gpios[3].name,"lid", GPIO_MAX_NAME_LENGTH);
+
+	/* Power Button */
+	gpios->gpios[4].port = 101;
+	gpios->gpios[4].polarity = ACTIVE_LOW;
+	gpios->gpios[4].value = (gen_pmcon_1 >> 9) & 1;
+	strncpy((char *)gpios->gpios[4].name,"power", GPIO_MAX_NAME_LENGTH);
+}
+#endif
+
+int get_developer_mode_switch(void)
+{
+	device_t dev;
+#ifdef __PRE_RAM__
+	dev = PCI_DEV(0, 0x1f, 2);
+#else
+	dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2));
+#endif
+	return (pci_read_config32(dev, SATA_SP) >> FLAG_DEV_MODE) & 1;
+}
+
+int get_recovery_mode_switch(void)
+{
+	device_t dev;
+#ifdef __PRE_RAM__
+	dev = PCI_DEV(0, 0x1f, 2);
+#else
+	dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2));
+#endif
+	return (pci_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1;
+}
+
+#ifdef __PRE_RAM__
+void save_chromeos_gpios(void)
+{
+	u16 gpio_base = pci_read_config32(PCH_LPC_DEV, GPIO_BASE) & 0xfffe;
+	u32 gp_lvl2 = inl(gpio_base + GP_LVL2);
+	u32 gp_lvl = inl(gpio_base + GP_LVL);
+	u32 flags = 0;
+
+	/* Write Protect: GPIO24 = KBC3_SPI_WP#, active high */
+	if (gp_lvl & (1 << GPIO_SPI_WP))
+		flags |= (1 << FLAG_SPI_WP);
+	/* Recovery: GPIO42 = CHP3_REC_MODE#, active low */
+	if (!(gp_lvl2 & (1 << (GPIO_REC_MODE-32))))
+		flags |= (1 << FLAG_REC_MODE);
+	/* Developer: GPIO17 = KBC3_DVP_MODE, active high */
+	if (gp_lvl & (1 << GPIO_DEV_MODE))
+		flags |= (1 << FLAG_DEV_MODE);
+
+	pci_write_config32(PCI_DEV(0, 0x1f, 2), SATA_SP, flags);
+}
+#endif
diff --git a/src/mainboard/samsung/lumpy/cmos.layout b/src/mainboard/samsung/lumpy/cmos.layout
new file mode 100644
index 0000000000..9552021aa8
--- /dev/null
+++ b/src/mainboard/samsung/lumpy/cmos.layout
@@ -0,0 +1,139 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+# -----------------------------------------------------------------
+entries
+
+#start-bit length  config config-ID    name
+#0            8       r       0        seconds
+#8            8       r       0        alarm_seconds
+#16           8       r       0        minutes
+#24           8       r       0        alarm_minutes
+#32           8       r       0        hours
+#40           8       r       0        alarm_hours
+#48           8       r       0        day_of_week
+#56           8       r       0        day_of_month
+#64           8       r       0        month
+#72           8       r       0        year
+# -----------------------------------------------------------------
+# Status Register A
+#80           4       r       0        rate_select
+#84           3       r       0        REF_Clock
+#87           1       r       0        UIP
+# -----------------------------------------------------------------
+# Status Register B
+#88           1       r       0        auto_switch_DST
+#89           1       r       0        24_hour_mode
+#90           1       r       0        binary_values_enable
+#91           1       r       0        square-wave_out_enable
+#92           1       r       0        update_finished_enable
+#93           1       r       0        alarm_interrupt_enable
+#94           1       r       0        periodic_interrupt_enable
+#95           1       r       0        disable_clock_updates
+# -----------------------------------------------------------------
+# Status Register C
+#96           4       r       0        status_c_rsvd
+#100          1       r       0        uf_flag
+#101          1       r       0        af_flag
+#102          1       r       0        pf_flag
+#103          1       r       0        irqf_flag
+# -----------------------------------------------------------------
+# Status Register D
+#104          7       r       0        status_d_rsvd
+#111          1       r       0        valid_cmos_ram
+# -----------------------------------------------------------------
+# Diagnostic Status Register
+#112          8       r       0        diag_rsvd1
+
+# -----------------------------------------------------------------
+0          120       r       0        reserved_memory
+#120        264       r       0        unused
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384          1       e       4        boot_option
+385          1       e       4        last_boot
+388          4       r       0        reboot_bits
+#390          2       r       0        unused?
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+392          3       e       5        baud_rate
+395          4       e       6        debug_level
+#399          1       r       0        unused
+
+# coreboot config options: cpu
+400          1       e       2        hyper_threading
+#401          7       r       0        unused
+
+# coreboot config options: southbridge
+408          1       e       1        nmi
+#409          2       e       7        power_on_after_fail
+#411          5       r       0        unused
+
+# coreboot config options: bootloader
+#Used by ChromeOS:
+416        128       r        0        vbnv
+#544        440       r       0        unused
+
+# SandyBridge MRC Scrambler Seed values
+896         32        r       0        mrc_scrambler_seed
+928         32        r       0        mrc_scrambler_seed_s3
+
+# coreboot config options: check sums
+984         16       h       0        check_sum
+#1000        24       r       0        amd_reserved
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value   text
+1     0     Disable
+1     1     Enable
+2     0     Enable
+2     1     Disable
+4     0     Fallback
+4     1     Normal
+5     0     115200
+5     1     57600
+5     2     38400
+5     3     19200
+5     4     9600
+5     5     4800
+5     6     2400
+5     7     1200
+6     1     Emergency
+6     2     Alert
+6     3     Critical
+6     4     Error
+6     5     Warning
+6     6     Notice
+6     7     Info
+6     8     Debug
+6     9     Spew
+7     0     Disable
+7     1     Enable
+7     2     Keep
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 415 984
+
+
diff --git a/src/mainboard/samsung/lumpy/devicetree.cb b/src/mainboard/samsung/lumpy/devicetree.cb
new file mode 100644
index 0000000000..36af1cae32
--- /dev/null
+++ b/src/mainboard/samsung/lumpy/devicetree.cb
@@ -0,0 +1,111 @@
+chip northbridge/intel/sandybridge
+
+	# Enable DisplayPort Hotplug with 6ms pulse
+	register "gpu_dp_d_hotplug" = "0x06"
+
+	# Enable Panel as LVDS and configure power delays
+	register "gpu_panel_port_select" = "0"			# LVDS
+	register "gpu_panel_power_cycle_delay" = "5"		# T4: 400ms
+	register "gpu_panel_power_up_delay" = "400"		# T1+T2: 40ms
+	register "gpu_panel_power_down_delay" = "150"		# T3: 15ms
+	register "gpu_panel_power_backlight_on_delay" = "2100"	# T5: 210ms
+	register "gpu_panel_power_backlight_off_delay" = "2100"	# TD: 210ms
+
+	device lapic_cluster 0 on
+		chip cpu/intel/socket_rPGA989
+			device lapic 0 on end
+		end
+		chip cpu/intel/model_206ax
+			# Magic APIC ID to locate this chip
+			device lapic 0xACAC off end
+
+			# Coordinate with HW_ALL
+			register "pstate_coord_type" = "0xfe"
+
+			register "c1_acpower" = "1"	# ACPI(C1) = MWAIT(C1)
+			register "c2_acpower" = "3"	# ACPI(C2) = MWAIT(C3)
+			register "c3_acpower" = "5"	# ACPI(C3) = MWAIT(C7)
+
+			register "c1_battery" = "1"	# ACPI(C1) = MWAIT(C1)
+			register "c2_battery" = "3"	# ACPI(C2) = MWAIT(C3)
+			register "c3_battery" = "5"	# ACPI(C3) = MWAIT(C7)
+		end
+	end
+
+	device pci_domain 0 on
+		device pci 00.0 on end # host bridge
+		device pci 02.0 on end # vga controller
+
+		chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
+			register "pirqa_routing" = "0x8b"
+			register "pirqb_routing" = "0x8a"
+			register "pirqc_routing" = "0x8b"
+			register "pirqd_routing" = "0x8b"
+			register "pirqe_routing" = "0x80"
+			register "pirqf_routing" = "0x80"
+			register "pirqg_routing" = "0x80"
+			register "pirqh_routing" = "0x80"
+
+			# GPI routing
+			#  0 No effect (default)
+			#  1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
+			#  2 SCI (if corresponding GPIO_EN bit is also set)
+			register "alt_gp_smi_en" = "0x0002"
+			register "gpi1_routing" = "1"
+			register "gpi7_routing" = "2"
+
+			register "ide_legacy_combined" = "0x0"
+			register "sata_ahci" = "0x1"
+			register "sata_port_map" = "0x1"
+
+			# EC range is 0xa00-0xa3f
+			register "gen1_dec" = "0x003c0a01"
+			register "gen2_dec" = "0x003c0b01"
+
+			device pci 16.0 on end # Management Engine Interface 1
+			device pci 16.1 off end # Management Engine Interface 2
+			device pci 16.2 off end # Management Engine IDE-R
+			device pci 16.3 off end # Management Engine KT
+			device pci 19.0 off end # Intel Gigabit Ethernet
+			device pci 1a.0 on end # USB2 EHCI #2
+			device pci 1b.0 on end # High Definition Audio
+			device pci 1c.0 on end # PCIe Port #1 (WLAN)
+			device pci 1c.1 off end # PCIe Port #2
+			device pci 1c.2 off end # PCIe Port #3
+			device pci 1c.3 on end # PCIe Port #4 (LAN)
+			device pci 1c.4 off end # PCIe Port #5
+			device pci 1c.5 off end # PCIe Port #6
+			device pci 1c.6 off end # PCIe Port #7
+			device pci 1c.7 off end # PCIe Port #8
+			device pci 1d.0 on end # USB2 EHCI #1
+			device pci 1e.0 off end # PCI bridge
+			device pci 1f.0 on # LPC bridge
+				chip superio/smsc/mec1308
+					device pnp 2e.1 on		# PM1
+						io 0x60 = 0xb00
+					end
+					device pnp 2e.2 off end		# EC1
+					device pnp 2e.3 off end		# EC2
+					device pnp 2e.4 off end		# UART
+					device pnp 2e.7 on		# KBC
+						irq 0x70 = 1
+					end
+					device pnp 2e.8 on		# EC0
+						io 0x60 = 0x62
+					end
+					device pnp 2e.9 on		# MBX
+						io 0x60 = 0xa00
+					end
+				end
+				chip ec/smsc/mec1308
+					register "mailbox_port" = "0xa00"
+					device pnp ff.1 off end
+				end
+			end
+			device pci 1f.2 on end # SATA Controller 1
+			device pci 1f.3 on end # SMBus
+			device pci 1f.5 off end # SATA Controller 2
+			device pci 1f.6 on end # Thermal
+		end
+	end
+end
diff --git a/src/mainboard/samsung/lumpy/dsdt.asl b/src/mainboard/samsung/lumpy/dsdt.asl
new file mode 100644
index 0000000000..94adfdaa3f
--- /dev/null
+++ b/src/mainboard/samsung/lumpy/dsdt.asl
@@ -0,0 +1,58 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	0x02,		// DSDT revision: ACPI v2.0
+	"COREv4",	// OEM id
+	"COREBOOT",     // OEM table id
+	0x20110725	// OEM revision
+)
+{
+	// Some generic macros
+	#include "acpi/platform.asl"
+
+	// global NVS and variables
+	#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
+
+	// General Purpose Events
+	//#include "acpi/gpe.asl"
+
+	// mainboard specific devices
+	#include "acpi/mainboard.asl"
+
+	#include <cpu/intel/model_206ax/acpi/cpu.asl>
+
+	#include "acpi/thermal.asl"
+
+	Scope (\_SB) {
+		Device (PCI0)
+		{
+			#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
+			#include <southbridge/intel/bd82x6x/acpi/pch.asl>
+		}
+	}
+
+	#include "acpi/chromeos.asl"
+
+	/* Chipset specific sleep states */
+	#include <southbridge/intel/bd82x6x/acpi/sleepstates.asl>
+}
diff --git a/src/mainboard/samsung/lumpy/ec.c b/src/mainboard/samsung/lumpy/ec.c
new file mode 100644
index 0000000000..40d831987d
--- /dev/null
+++ b/src/mainboard/samsung/lumpy/ec.c
@@ -0,0 +1,44 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/acpi.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+#include <types.h>
+#include <console/console.h>
+#include <ec/smsc/mec1308/ec.h>
+#include "ec.h"
+
+void lumpy_ec_init(void)
+{
+	printk(BIOS_DEBUG, "lumpy_ec_init\n");
+
+	if (acpi_slp_type == 3)
+		return;
+
+	/*
+	 * Enable EC control of fan speed.
+	 *
+	 * This will be changed to OS control in ACPI EC _REG
+	 * method when the OS is ready to control the fan.
+	 */
+	ec_write(EC_FAN_SPEED, 0);
+
+	send_ec_command_data(EC_BATTERY_MODE, EC_BATTERY_MODE_NORMAL);
+	send_ec_command_data(EC_POWER_BUTTON_MODE, EC_POWER_BUTTON_MODE_OS);
+}
diff --git a/src/mainboard/samsung/lumpy/ec.h b/src/mainboard/samsung/lumpy/ec.h
new file mode 100644
index 0000000000..3f90211e78
--- /dev/null
+++ b/src/mainboard/samsung/lumpy/ec.h
@@ -0,0 +1,61 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef LUMPY_EC_H
+#define LUMPY_EC_H
+
+#define EC_MAILBOX_PORT               0xa00 /* Mailbox IO address */
+#define EC_SMI_GPI                    1     /* GPIO 1 is KBC3_EXTSMI# */
+
+/* Commands */
+#define EC_SMI_ENABLE                 0x74
+#define EC_SMI_DISABLE                0x75
+#define EC_ACPI_ENABLE                0x76 /* Enter ACPI mode */
+#define EC_ACPI_DISABLE               0x77 /* Exit ACPI mode */
+
+/* Commands with data */
+#define EC_AUX_PORT_MODE              0x64 /* PS/2 control mode */
+#define  EC_AUX_PORT_MODE_ENABLE       0x00
+#define  EC_AUX_PORT_MODE_DISABLE      0x01
+#define EC_POWER_BUTTON_MODE          0x63
+#define  EC_POWER_BUTTON_MODE_OS       0x00 /* OS control, 8 second override */
+#define  EC_POWER_BUTTON_MODE_EC       0x01 /* EC control */
+#define EC_BACKLIGHT_OFF              0x67  /* Turn Backlight Off */
+#define EC_BACKLIGHT_ON               0x68  /* Turn Backlight On */
+#define EC_BATTERY_MODE               0x13
+#define  EC_BATTERY_MODE_NORMAL        0x00 /* Normal mode */
+#define  EC_BATTERY_MODE_EXTEND        0x01 /* Battery Life Cycle Extension */
+#define EC_GET_SMI_CAUSE              0x72  /* Get cause of SMI */
+
+/* EC RAM */
+#define EC_FAN_SPEED                  0xca
+#define  EC_FAN_SPEED_LEVEL_0	       0x01 /* Level 0 is fastest */
+#define  EC_FAN_SPEED_LEVEL_1	       0x02 /* Level 1 is fast */
+#define  EC_FAN_SPEED_LEVEL_2	       0x04 /* Level 2 is slow */
+#define  EC_FAN_SPEED_LEVEL_3	       0x08 /* Level 3 is slowest */
+#define  EC_FAN_SPEED_LEVEL_4	       0x10 /* Level 4 is off */
+#define  EC_FAN_SPEED_FLAG_OS          0x80 /* OS control of fan speed */
+
+/* EC SMI */
+#define EC_LID_CLOSE                  0x9c  /* Lid close event */
+#define EC_LID_OPEN                   0x9d  /* Lid open event */
+
+extern void lumpy_ec_init(void);
+
+#endif // LUMPY_EC_H
diff --git a/src/mainboard/samsung/lumpy/fadt.c b/src/mainboard/samsung/lumpy/fadt.c
new file mode 100644
index 0000000000..6d78233a41
--- /dev/null
+++ b/src/mainboard/samsung/lumpy/fadt.c
@@ -0,0 +1,156 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <string.h>
+#include <device/pci.h>
+#include <arch/acpi.h>
+#include <cpu/x86/smm.h>
+
+void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
+{
+	acpi_header_t *header = &(fadt->header);
+	u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)),
+								0x40) & 0xfffe;
+
+	memset((void *) fadt, 0, sizeof(acpi_fadt_t));
+	memcpy(header->signature, "FACP", 4);
+	header->length = sizeof(acpi_fadt_t);
+	header->revision = 3;
+	memcpy(header->oem_id, OEM_ID, 6);
+	memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
+	memcpy(header->asl_compiler_id, ASLC, 4);
+	header->asl_compiler_revision = 1;
+
+	fadt->firmware_ctrl = (unsigned long) facs;
+	fadt->dsdt = (unsigned long) dsdt;
+	fadt->model = 1;
+	fadt->preferred_pm_profile = PM_MOBILE;
+
+	fadt->sci_int = 0x9;
+	fadt->smi_cmd = APM_CNT;
+	fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
+	fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
+	fadt->s4bios_req = 0x0;
+	fadt->pstate_cnt = APM_CNT_PST_CONTROL;
+
+	fadt->pm1a_evt_blk = pmbase;
+	fadt->pm1b_evt_blk = 0x0;
+	fadt->pm1a_cnt_blk = pmbase + 0x4;
+	fadt->pm1b_cnt_blk = 0x0;
+	fadt->pm2_cnt_blk = pmbase + 0x50;
+	fadt->pm_tmr_blk = pmbase + 0x8;
+	fadt->gpe0_blk = pmbase + 0x20;
+	fadt->gpe1_blk = 0;
+
+	fadt->pm1_evt_len = 4;
+	fadt->pm1_cnt_len = 2;
+	fadt->pm2_cnt_len = 1;
+	fadt->pm_tmr_len = 4;
+	fadt->gpe0_blk_len = 16;
+	fadt->gpe1_blk_len = 0;
+	fadt->gpe1_base = 0;
+	fadt->cst_cnt = APM_CNT_CST_CONTROL;
+	fadt->p_lvl2_lat = 1;
+	fadt->p_lvl3_lat = 87;
+	fadt->flush_size = 1024;
+	fadt->flush_stride = 16;
+	fadt->duty_offset = 1;
+	fadt->duty_width = 0;
+	fadt->day_alrm = 0xd;
+	fadt->mon_alrm = 0x00;
+	fadt->century = 0x00;
+	fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
+
+	fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
+			ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
+			ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE |
+			ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK;
+
+	fadt->reset_reg.space_id = 1;
+	fadt->reset_reg.bit_width = 8;
+	fadt->reset_reg.bit_offset = 0;
+	fadt->reset_reg.resv = 0;
+	fadt->reset_reg.addrl = 0xcf9;
+	fadt->reset_reg.addrh = 0;
+
+	fadt->reset_value = 6;
+	fadt->x_firmware_ctl_l = (unsigned long)facs;
+	fadt->x_firmware_ctl_h = 0;
+	fadt->x_dsdt_l = (unsigned long)dsdt;
+	fadt->x_dsdt_h = 0;
+
+	fadt->x_pm1a_evt_blk.space_id = 1;
+	fadt->x_pm1a_evt_blk.bit_width = 32;
+	fadt->x_pm1a_evt_blk.bit_offset = 0;
+	fadt->x_pm1a_evt_blk.resv = 0;
+	fadt->x_pm1a_evt_blk.addrl = pmbase;
+	fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_evt_blk.space_id = 1;
+	fadt->x_pm1b_evt_blk.bit_width = 0;
+	fadt->x_pm1b_evt_blk.bit_offset = 0;
+	fadt->x_pm1b_evt_blk.resv = 0;
+	fadt->x_pm1b_evt_blk.addrl = 0x0;
+	fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1a_cnt_blk.space_id = 1;
+	fadt->x_pm1a_cnt_blk.bit_width = 16;
+	fadt->x_pm1a_cnt_blk.bit_offset = 0;
+	fadt->x_pm1a_cnt_blk.resv = 0;
+	fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
+	fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_cnt_blk.space_id = 1;
+	fadt->x_pm1b_cnt_blk.bit_width = 0;
+	fadt->x_pm1b_cnt_blk.bit_offset = 0;
+	fadt->x_pm1b_cnt_blk.resv = 0;
+	fadt->x_pm1b_cnt_blk.addrl = 0x0;
+	fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm2_cnt_blk.space_id = 1;
+	fadt->x_pm2_cnt_blk.bit_width = 8;
+	fadt->x_pm2_cnt_blk.bit_offset = 0;
+	fadt->x_pm2_cnt_blk.resv = 0;
+	fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50;
+	fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm_tmr_blk.space_id = 1;
+	fadt->x_pm_tmr_blk.bit_width = 32;
+	fadt->x_pm_tmr_blk.bit_offset = 0;
+	fadt->x_pm_tmr_blk.resv = 0;
+	fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
+	fadt->x_pm_tmr_blk.addrh = 0x0;
+
+	fadt->x_gpe0_blk.space_id = 1;
+	fadt->x_gpe0_blk.bit_width = 64;
+	fadt->x_gpe0_blk.bit_offset = 0;
+	fadt->x_gpe0_blk.resv = 0;
+	fadt->x_gpe0_blk.addrl = pmbase + 0x20;
+	fadt->x_gpe0_blk.addrh = 0x0;
+
+	fadt->x_gpe1_blk.space_id = 1;
+	fadt->x_gpe1_blk.bit_width = 0;
+	fadt->x_gpe1_blk.bit_offset = 0;
+	fadt->x_gpe1_blk.resv = 0;
+	fadt->x_gpe1_blk.addrl = 0x0;
+	fadt->x_gpe1_blk.addrh = 0x0;
+
+	header->checksum =
+	    acpi_checksum((void *) fadt, header->length);
+}
diff --git a/src/mainboard/samsung/lumpy/gpio.h b/src/mainboard/samsung/lumpy/gpio.h
new file mode 100644
index 0000000000..af5f3e24d0
--- /dev/null
+++ b/src/mainboard/samsung/lumpy/gpio.h
@@ -0,0 +1,336 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef LUMPY_GPIO_H
+#define LUMPY_GPIO_H
+
+#include "southbridge/intel/bd82x6x/gpio.h"
+
+/*
+ * GPIO SET 1 includes GPIO0 to GPIO31
+ */
+
+const struct pch_gpio_set1 pch_gpio_set1_mode = {
+	.gpio0  = GPIO_MODE_GPIO,	/* CHP3_SERDBG */
+	.gpio1  = GPIO_MODE_GPIO,	/* KBC3_EXTSMI# */
+	.gpio2  = GPIO_MODE_NATIVE,	/* CHP3_ALSINT# (Light Sensor) */
+	.gpio3  = GPIO_MODE_NATIVE,	/* CHP3_TP_INT# (Trackpad) */
+	.gpio4  = GPIO_MODE_NONE,
+	.gpio5  = GPIO_MODE_GPIO,	/* SIM3_CARD_DET# */
+	.gpio6  = GPIO_MODE_NONE,
+	.gpio7  = GPIO_MODE_GPIO,	/* KBC3_RUNSCI# */
+	.gpio8  = GPIO_MODE_GPIO,	/* CHP3_INTELBT_OFF# */
+	.gpio9  = GPIO_MODE_NONE,
+	.gpio10 = GPIO_MODE_NONE,
+	.gpio11 = GPIO_MODE_GPIO,	/* CHP3_TP_INT# (Trackpad wake) */
+	.gpio12 = GPIO_MODE_NONE,
+	.gpio13 = GPIO_MODE_GPIO,	/* CHP3_DEBUG13 */
+	.gpio14 = GPIO_MODE_GPIO,	/* KBC3_WAKESCI# */
+	.gpio15 = GPIO_MODE_NONE,
+	.gpio16 = GPIO_MODE_NONE,
+	.gpio17 = GPIO_MODE_GPIO,	/* KBC3_DVP_MODE */
+	.gpio18 = GPIO_MODE_NATIVE,	/* MIN3_CLKREQ1# */
+	.gpio19 = GPIO_MODE_NONE,
+	.gpio20 = GPIO_MODE_NONE,
+	.gpio21 = GPIO_MODE_GPIO,	/* LCD3_SIZE */
+	.gpio22 = GPIO_MODE_GPIO,	/* CHP3_BIOS_CRISIS# */
+	.gpio23 = GPIO_MODE_NONE,
+	.gpio24 = GPIO_MODE_GPIO,	/* KBC3_SPI_WP# */
+	.gpio25 = GPIO_MODE_NONE,
+	.gpio26 = GPIO_MODE_NATIVE,	/* LAN3_CLKREQ# */
+	.gpio27 = GPIO_MODE_NONE,
+	.gpio28 = GPIO_MODE_NONE,
+	.gpio29 = GPIO_MODE_NONE,
+	.gpio30 = GPIO_MODE_NATIVE,	/* CHP3_SUSWARN# */
+	.gpio31 = GPIO_MODE_NATIVE,	/* KBC3_AC_PRESENT */
+};
+
+const struct pch_gpio_set1 pch_gpio_set1_direction = {
+	.gpio0  = GPIO_DIR_OUTPUT,
+	.gpio1  = GPIO_DIR_INPUT,
+	.gpio2  = GPIO_DIR_INPUT,
+	.gpio3  = GPIO_DIR_INPUT,
+	.gpio4  = GPIO_DIR_INPUT,
+	.gpio5  = GPIO_DIR_INPUT,
+	.gpio6  = GPIO_DIR_INPUT,
+	.gpio7  = GPIO_DIR_INPUT,
+	.gpio8  = GPIO_DIR_OUTPUT,
+	.gpio9  = GPIO_DIR_INPUT,
+	.gpio10 = GPIO_DIR_INPUT,
+	.gpio11 = GPIO_DIR_INPUT,
+	.gpio12 = GPIO_DIR_INPUT,
+	.gpio13 = GPIO_DIR_INPUT,
+	.gpio14 = GPIO_DIR_INPUT,
+	.gpio15 = GPIO_DIR_INPUT,
+	.gpio16 = GPIO_DIR_INPUT,
+	.gpio17 = GPIO_DIR_INPUT,
+	.gpio18 = GPIO_DIR_INPUT,
+	.gpio19 = GPIO_DIR_INPUT,
+	.gpio20 = GPIO_DIR_INPUT,
+	.gpio21 = GPIO_DIR_INPUT,
+	.gpio22 = GPIO_DIR_OUTPUT,
+	.gpio23 = GPIO_DIR_INPUT,
+	.gpio24 = GPIO_DIR_INPUT,
+	.gpio25 = GPIO_DIR_INPUT,
+	.gpio26 = GPIO_DIR_INPUT,
+	.gpio27 = GPIO_DIR_INPUT,
+	.gpio28 = GPIO_DIR_INPUT,
+	.gpio29 = GPIO_DIR_INPUT,
+	.gpio30 = GPIO_DIR_INPUT,
+	.gpio31 = GPIO_DIR_INPUT,
+};
+
+const struct pch_gpio_set1 pch_gpio_set1_level = {
+	.gpio0  = GPIO_LEVEL_LOW,
+	.gpio1  = GPIO_LEVEL_LOW,
+	.gpio2  = GPIO_LEVEL_LOW,
+	.gpio3  = GPIO_LEVEL_LOW,
+	.gpio4  = GPIO_LEVEL_LOW,
+	.gpio5  = GPIO_LEVEL_LOW,
+	.gpio6  = GPIO_LEVEL_LOW,
+	.gpio7  = GPIO_LEVEL_LOW,
+	.gpio8  = GPIO_LEVEL_LOW,
+	.gpio9  = GPIO_LEVEL_LOW,
+	.gpio10 = GPIO_LEVEL_LOW,
+	.gpio11 = GPIO_LEVEL_LOW,
+	.gpio12 = GPIO_LEVEL_LOW,
+	.gpio13 = GPIO_LEVEL_LOW,
+	.gpio14 = GPIO_LEVEL_LOW,
+	.gpio15 = GPIO_LEVEL_LOW,
+	.gpio16 = GPIO_LEVEL_LOW,
+	.gpio17 = GPIO_LEVEL_LOW,
+	.gpio18 = GPIO_LEVEL_LOW,
+	.gpio19 = GPIO_LEVEL_LOW,
+	.gpio20 = GPIO_LEVEL_LOW,
+	.gpio21 = GPIO_LEVEL_LOW,
+	.gpio22 = GPIO_LEVEL_HIGH,
+	.gpio23 = GPIO_LEVEL_LOW,
+	.gpio24 = GPIO_LEVEL_LOW,
+	.gpio25 = GPIO_LEVEL_LOW,
+	.gpio26 = GPIO_LEVEL_LOW,
+	.gpio27 = GPIO_LEVEL_LOW,
+	.gpio28 = GPIO_LEVEL_LOW,
+	.gpio29 = GPIO_LEVEL_LOW,
+	.gpio30 = GPIO_LEVEL_LOW,
+	.gpio31 = GPIO_LEVEL_LOW,
+};
+
+const struct pch_gpio_set1 pch_gpio_set1_invert = {
+	.gpio0  = GPIO_NO_INVERT,
+	.gpio1  = GPIO_INVERT,
+	.gpio2  = GPIO_INVERT,
+	.gpio3  = GPIO_INVERT,
+	.gpio4  = GPIO_NO_INVERT,
+	.gpio5  = GPIO_INVERT,
+	.gpio6  = GPIO_NO_INVERT,
+	.gpio7  = GPIO_INVERT,
+	.gpio8  = GPIO_NO_INVERT,
+	.gpio9  = GPIO_NO_INVERT,
+	.gpio10 = GPIO_NO_INVERT,
+	.gpio11 = GPIO_INVERT,
+	.gpio12 = GPIO_NO_INVERT,
+	.gpio13 = GPIO_NO_INVERT,
+	.gpio14 = GPIO_INVERT,
+	.gpio15 = GPIO_NO_INVERT,
+};
+
+/*
+ * GPIO SET 2 includes GPIO32 to GPIO63
+ */
+
+const struct pch_gpio_set2 pch_gpio_set2_mode = {
+	.gpio32 = GPIO_MODE_NATIVE,	/* PCI3_CLKRUN# */
+	.gpio33 = GPIO_MODE_GPIO,	/* Onboard Memory Capacity */
+	.gpio34 = GPIO_MODE_NONE,
+	.gpio35 = GPIO_MODE_GPIO,	/* CHP3_WLAN_OFF# */
+	.gpio36 = GPIO_MODE_NONE,
+	.gpio37 = GPIO_MODE_GPIO,	/* CHP3_FDI_OVRVLTG */
+	.gpio38 = GPIO_MODE_GPIO,	/* CHP3_3G_OFF# */
+	.gpio39 = GPIO_MODE_NONE,
+	.gpio40 = GPIO_MODE_NATIVE,	/* USB3_OC1# */
+	.gpio41 = GPIO_MODE_GPIO,	/* Onboard Memory Revision */
+	.gpio42 = GPIO_MODE_GPIO,	/* CHP3_REC_MODE# */
+	.gpio43 = GPIO_MODE_GPIO,	/* CHP3_HSPA_PWRON# */
+	.gpio44 = GPIO_MODE_GPIO,	/* CHP3_SMRT_CHG0_CTL2# */
+	.gpio45 = GPIO_MODE_GPIO,	/* CHP3_SMRT_CHG0_CTL3# */
+	.gpio46 = GPIO_MODE_GPIO,	/* CHP3_SMRT_CHG1_CTL2# */
+	.gpio47 = GPIO_MODE_GPIO,	/* CHP3_CHG_ENABLE0 */
+	.gpio48 = GPIO_MODE_GPIO,	/* CHP3_BT_OFF# */
+	.gpio49 = GPIO_MODE_GPIO,	/* Onboard Memory Vendor */
+	.gpio50 = GPIO_MODE_NONE,
+	.gpio51 = GPIO_MODE_NONE,
+	.gpio52 = GPIO_MODE_NONE,
+	.gpio53 = GPIO_MODE_NATIVE,
+	.gpio54 = GPIO_MODE_NONE,
+	.gpio55 = GPIO_MODE_GPIO,	/* STP_A16OVR */
+	.gpio56 = GPIO_MODE_GPIO,	/* CHP3_CHG_ENABLE1 */
+	.gpio57 = GPIO_MODE_GPIO,	/* CHP3_DEBUG10 */
+	.gpio58 = GPIO_MODE_NATIVE,	/* SIO3_THERM_SMCLK# */
+	.gpio59 = GPIO_MODE_NATIVE,	/* USB3_OC0# */
+	.gpio60 = GPIO_MODE_GPIO,	/* CHP3_DRAMRST_GATE */
+	.gpio61 = GPIO_MODE_NATIVE,	/* CHP3_SUSSTAT# */
+	.gpio62 = GPIO_MODE_NATIVE,	/* CHP3_SUSCLK */
+	.gpio63 = GPIO_MODE_NATIVE,	/* CHP3_SLPS5# */
+};
+
+const struct pch_gpio_set2 pch_gpio_set2_direction = {
+	.gpio32 = GPIO_DIR_INPUT,
+	.gpio33 = GPIO_DIR_INPUT,
+	.gpio34 = GPIO_DIR_INPUT,
+	.gpio35 = GPIO_DIR_OUTPUT,
+	.gpio36 = GPIO_DIR_INPUT,
+	.gpio37 = GPIO_DIR_INPUT,
+	.gpio38 = GPIO_DIR_OUTPUT,
+	.gpio39 = GPIO_DIR_INPUT,
+	.gpio40 = GPIO_DIR_INPUT,
+	.gpio41 = GPIO_DIR_INPUT,
+	.gpio42 = GPIO_DIR_INPUT,
+	.gpio43 = GPIO_DIR_OUTPUT,
+	.gpio44 = GPIO_DIR_OUTPUT,
+	.gpio45 = GPIO_DIR_OUTPUT,
+	.gpio46 = GPIO_DIR_OUTPUT,
+	.gpio47 = GPIO_DIR_OUTPUT,
+	.gpio48 = GPIO_DIR_OUTPUT,
+	.gpio49 = GPIO_DIR_INPUT,
+	.gpio50 = GPIO_DIR_INPUT,
+	.gpio51 = GPIO_DIR_INPUT,
+	.gpio52 = GPIO_DIR_INPUT,
+	.gpio53 = GPIO_DIR_INPUT,
+	.gpio54 = GPIO_DIR_INPUT,
+	.gpio55 = GPIO_DIR_INPUT,
+	.gpio56 = GPIO_DIR_OUTPUT,
+	.gpio57 = GPIO_DIR_OUTPUT,
+	.gpio58 = GPIO_DIR_INPUT,
+	.gpio59 = GPIO_DIR_INPUT,
+	.gpio60 = GPIO_DIR_OUTPUT,
+	.gpio61 = GPIO_DIR_INPUT,
+	.gpio62 = GPIO_DIR_INPUT,
+	.gpio63 = GPIO_DIR_INPUT,
+};
+
+const struct pch_gpio_set2 pch_gpio_set2_level = {
+	.gpio32 = GPIO_LEVEL_LOW,
+	.gpio33 = GPIO_LEVEL_LOW,
+	.gpio34 = GPIO_LEVEL_LOW,
+	.gpio35 = GPIO_LEVEL_HIGH,	/* Enable WLAN */
+	.gpio36 = GPIO_LEVEL_LOW,
+	.gpio37 = GPIO_LEVEL_LOW,
+	.gpio38 = GPIO_LEVEL_HIGH,	/* Enable 3G */
+	.gpio39 = GPIO_LEVEL_LOW,
+	.gpio40 = GPIO_LEVEL_LOW,
+	.gpio41 = GPIO_LEVEL_LOW,
+	.gpio42 = GPIO_LEVEL_LOW,
+	.gpio43 = GPIO_LEVEL_LOW,
+	.gpio44 = GPIO_LEVEL_HIGH,	/* CTL2=1 for USB0 SDP */
+	.gpio45 = GPIO_LEVEL_LOW,	/* CTL3=0 for USB0 SDP */
+	.gpio46 = GPIO_LEVEL_HIGH,	/* CTL2=1 for USB1 SDP */
+	.gpio47 = GPIO_LEVEL_HIGH,	/* Enable USB0 */
+	.gpio48 = GPIO_LEVEL_LOW,	/* Disable Bluetooth */
+	.gpio49 = GPIO_LEVEL_LOW,
+	.gpio50 = GPIO_LEVEL_LOW,
+	.gpio51 = GPIO_LEVEL_LOW,
+	.gpio52 = GPIO_LEVEL_LOW,
+	.gpio53 = GPIO_LEVEL_LOW,
+	.gpio54 = GPIO_LEVEL_LOW,
+	.gpio55 = GPIO_LEVEL_LOW,
+	.gpio56 = GPIO_LEVEL_HIGH,	/* Enable USB1 */
+	.gpio57 = GPIO_LEVEL_LOW,
+	.gpio58 = GPIO_LEVEL_LOW,
+	.gpio59 = GPIO_LEVEL_LOW,
+	.gpio60 = GPIO_LEVEL_HIGH,
+	.gpio61 = GPIO_LEVEL_LOW,
+	.gpio62 = GPIO_LEVEL_LOW,
+	.gpio63 = GPIO_LEVEL_LOW,
+};
+
+/*
+ * GPIO SET 3 includes GPIO64 to GPIO75
+ */
+
+const struct pch_gpio_set3 pch_gpio_set3_mode = {
+	.gpio64 = GPIO_MODE_NONE,
+	.gpio65 = GPIO_MODE_NONE,
+	.gpio66 = GPIO_MODE_NONE,
+	.gpio67 = GPIO_MODE_NONE,
+	.gpio68 = GPIO_MODE_NONE,
+	.gpio69 = GPIO_MODE_GPIO,	/* PEX3_WWAN_DET# */
+	.gpio70 = GPIO_MODE_GPIO,	/* CHP3_WLAN_RST# */
+	.gpio71 = GPIO_MODE_GPIO,	/* CHP3_WLAN_PWRON */
+	.gpio72 = GPIO_MODE_NATIVE,	/* BATLOW# (pullup) */
+	.gpio73 = GPIO_MODE_GPIO,	/* CHP3_SMRT_CHG1_CTL3# */
+	.gpio74 = GPIO_MODE_NONE,
+	.gpio75 = GPIO_MODE_NATIVE,	/* SIO3_THERM_SMDATA# */
+};
+
+const struct pch_gpio_set3 pch_gpio_set3_direction = {
+	.gpio64 = GPIO_DIR_INPUT,
+	.gpio65 = GPIO_DIR_INPUT,
+	.gpio66 = GPIO_DIR_INPUT,
+	.gpio67 = GPIO_DIR_INPUT,
+	.gpio68 = GPIO_DIR_INPUT,
+	.gpio69 = GPIO_DIR_INPUT,
+	.gpio70 = GPIO_DIR_OUTPUT,
+	.gpio71 = GPIO_DIR_OUTPUT,
+	.gpio72 = GPIO_DIR_INPUT,
+	.gpio73 = GPIO_DIR_OUTPUT,
+	.gpio74 = GPIO_DIR_INPUT,
+	.gpio75 = GPIO_DIR_INPUT,
+};
+
+const struct pch_gpio_set3 pch_gpio_set3_level = {
+	.gpio64 = GPIO_LEVEL_LOW,
+	.gpio65 = GPIO_LEVEL_LOW,
+	.gpio66 = GPIO_LEVEL_LOW,
+	.gpio67 = GPIO_LEVEL_LOW,
+	.gpio68 = GPIO_LEVEL_LOW,
+	.gpio69 = GPIO_LEVEL_LOW,
+	.gpio70 = GPIO_LEVEL_HIGH,	/* WLAN out of reset */
+	.gpio71 = GPIO_LEVEL_HIGH,	/* WLAN power on */
+	.gpio72 = GPIO_LEVEL_LOW,
+	.gpio73 = GPIO_LEVEL_LOW,	/* USB1 CTL3=0 for SDP */
+	.gpio74 = GPIO_LEVEL_LOW,
+	.gpio75 = GPIO_LEVEL_LOW,
+};
+
+const struct pch_gpio_set2 pch_gpio_set2_reset = {
+	.gpio38 = GPIO_RESET_RSMRST,
+	.gpio43 = GPIO_RESET_RSMRST,
+};
+
+const struct pch_gpio_map lumpy_gpio_map = {
+	.set1 = {
+		.mode      = &pch_gpio_set1_mode,
+		.direction = &pch_gpio_set1_direction,
+		.level     = &pch_gpio_set1_level,
+		.invert    = &pch_gpio_set1_invert,
+	},
+	.set2 = {
+		.mode      = &pch_gpio_set2_mode,
+		.direction = &pch_gpio_set2_direction,
+		.level     = &pch_gpio_set2_level,
+		.reset     = &pch_gpio_set2_reset,
+	},
+	.set3 = {
+		.mode      = &pch_gpio_set3_mode,
+		.direction = &pch_gpio_set3_direction,
+		.level     = &pch_gpio_set3_level,
+	},
+};
+
+#endif
diff --git a/src/mainboard/samsung/lumpy/hda_verb.h b/src/mainboard/samsung/lumpy/hda_verb.h
new file mode 100644
index 0000000000..732f0aad5f
--- /dev/null
+++ b/src/mainboard/samsung/lumpy/hda_verb.h
@@ -0,0 +1,71 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (c) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+static const u32 mainboard_cim_verb_data[] = {
+	/* coreboot specific header */
+	0x10134210,	// Codec Vendor / Device ID: Realtek ALC262
+	0x144db082,	// Subsystem ID
+	0x00000007,	// Number of jacks
+
+	/* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x144dc0c2 */
+	0x00172082,
+	0x001721b0,
+	0x0017224d,
+	0x00172314,
+
+	0x00170500,
+
+	/* Pin Widget Verb Table */
+
+	/* Pin Complex (NID 0x05) */
+	0x00571cf0,
+	0x00571d10,
+	0x00571e21,
+	0x00571f02,
+
+	/* Pin Complex (NID 0x06) */
+	0x00671cf0,
+	0x00671d00,
+	0x00671e17,
+	0x00671f90,
+
+	/* Pin Complex (NID 0x07) */
+	0x00771cf0,
+	0x00771d10,
+	0x00771ea1,
+	0x00771f02,
+
+	/* Pin Complex (NID 0x08) */
+	0x00871c37,
+	0x00871d00,
+	0x00871ea7,
+	0x00871f77,
+
+	/* Pin Complex (NID 0x09) */
+	0x00971c3e,
+	0x00971d00,
+	0x00971ea6,
+	0x00971fb7,
+
+	/* Pin Complex (NID 0x0a) */
+	0x00a71cf0,
+	0x00a71d10,
+	0x00a71e45,
+	0x00a71f43
+};
diff --git a/src/mainboard/samsung/lumpy/mainboard.c b/src/mainboard/samsung/lumpy/mainboard.c
new file mode 100644
index 0000000000..c5db0d3582
--- /dev/null
+++ b/src/mainboard/samsung/lumpy/mainboard.c
@@ -0,0 +1,332 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <string.h>
+#include <device/device.h>
+#include <device/pci_def.h>
+#include <device/pci_ops.h>
+#include <console/console.h>
+#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL
+#include <x86emu/x86emu.h>
+#endif
+#include <pc80/mc146818rtc.h>
+#include <arch/acpi.h>
+#include <arch/io.h>
+#include <arch/interrupt.h>
+#include <arch/coreboot_tables.h>
+#include <ec/smsc/mec1308/ec.h>
+#include "hda_verb.h"
+#include "chip.h"
+#include "ec.h"
+#include "onboard.h"
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <smbios.h>
+
+void mainboard_suspend_resume(void)
+{
+	/* Call SMM finalize() handlers before resume */
+	outb(0xcb, 0xb2);
+
+	/* Enable EC ACPI mode for the OS before resume */
+	send_ec_command(EC_SMI_DISABLE);
+	send_ec_command(EC_ACPI_ENABLE);
+}
+
+int add_mainboard_resources(struct lb_memory *mem)
+{
+	return add_northbridge_resources(mem);
+}
+
+#if defined(CONFIG_PCI_OPTION_ROM_RUN_REALMODE) && CONFIG_PCI_OPTION_ROM_RUN_REALMODE
+static int int15_handler(struct eregs *regs)
+{
+	int res=-1;
+
+	printk(BIOS_DEBUG, "%s: INT15 function %04x!\n",
+			__func__, regs->eax & 0xffff);
+
+	switch(regs->eax & 0xffff) {
+	case 0x5f34:
+		/*
+		 * Set Panel Fitting Hook:
+		 *  bit 2 = Graphics Stretching
+		 *  bit 1 = Text Stretching
+		 *  bit 0 = Centering (do not set with bit1 or bit2)
+		 *  0     = video bios default
+		 */
+		regs->eax &= 0xffff0000;
+		regs->eax |= 0x005f;
+		regs->ecx &= 0xffffff00;
+		regs->ecx |= 0x00;
+		res = 0;
+		break;
+	case 0x5f35:
+		/*
+		 * Boot Display Device Hook:
+		 *  bit 0 = CRT
+		 *  bit 1 = TV
+		 *  bit 2 = EFP *
+		 *  bit 3 = LFP
+		 *  bit 4 = CRT2
+		 *  bit 5 = TV2
+		 *  bit 6 = EFP2 *
+		 *  bit 7 = LFP2
+		 */
+		regs->eax &= 0xffff0000;
+		regs->eax |= 0x005f;
+		regs->ecx &= 0xffff0000;
+		regs->ecx |= 0x0000;
+		res = 0;
+		break;
+	case 0x5f51:
+		/*
+		 * Hook to select active LFP configuration:
+		 *  00h = No LVDS, VBIOS does not enable LVDS
+		 *  01h = Int-LVDS, LFP driven by integrated LVDS decoder
+		 *  02h = SVDO-LVDS, LFP driven by SVDO decoder
+		 *  03h = eDP, LFP Driven by Int-DisplayPort encoder
+		 */
+		regs->eax &= 0xffff0000;
+		regs->eax |= 0x005f;
+		regs->ecx &= 0xffff0000;
+		regs->ecx |= 0x0001;
+		res = 0;
+		break;
+	case 0x5f70:
+		switch ((regs->ecx >> 8) & 0xff) {
+		case 0:
+			/* Get Mux */
+			regs->eax &= 0xffff0000;
+			regs->eax |= 0x005f;
+			regs->ecx &= 0xffff0000;
+			regs->ecx |= 0x0000;
+			res = 0;
+			break;
+		case 1:
+			/* Set Mux */
+			regs->eax &= 0xffff0000;
+			regs->eax |= 0x005f;
+			regs->ecx &= 0xffff0000;
+			regs->ecx |= 0x0000;
+			res = 0;
+			break;
+		case 2:
+			/* Get SG/Non-SG mode */
+			regs->eax &= 0xffff0000;
+			regs->eax |= 0x005f;
+			regs->ecx &= 0xffff0000;
+			regs->ecx |= 0x0000;
+			res = 0;
+			break;
+		default:
+			/* Interrupt was not handled */
+			printk(BIOS_DEBUG, "Unknown INT15 5f70 function: 0x%02x\n",
+				((regs->ecx >> 8) & 0xff));
+			return 0;
+		}
+		break;
+
+        default:
+		printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n",
+				regs->eax & 0xffff);
+		break;
+	}
+	return res;
+}
+#endif
+
+#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL
+static int int15_handler(void)
+{
+	printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n",
+			  __func__, M.x86.R_AX, M.x86.R_BX, M.x86.R_CX, M.x86.R_DX);
+
+	switch (M.x86.R_AX) {
+	case 0x5f34:
+		/*
+		 * Set Panel Fitting Hook:
+		 *  bit 2 = Graphics Stretching
+		 *  bit 1 = Text Stretching
+		 *  bit 0 = Centering (do not set with bit1 or bit2)
+		 *  0     = video bios default
+		 */
+		M.x86.R_AX = 0x005f;
+		M.x86.R_CL = 0x00;
+		break;
+	case 0x5f35:
+		/*
+		 * Boot Display Device Hook:
+		 *  bit 0 = CRT
+		 *  bit 1 = TV
+		 *  bit 2 = EFP *
+		 *  bit 3 = LFP
+		 *  bit 4 = CRT2
+		 *  bit 5 = TV2
+		 *  bit 6 = EFP2 *
+		 *  bit 7 = LFP2
+		 */
+		M.x86.R_AX = 0x005f;
+		M.x86.R_CX = 0x0000;
+		break;
+	case 0x5f51:
+		/*
+		 * Hook to select active LFP configuration:
+		 *  00h = No LVDS, VBIOS does not enable LVDS
+		 *  01h = Int-LVDS, LFP driven by integrated LVDS decoder
+		 *  02h = SVDO-LVDS, LFP driven by SVDO decoder
+		 *  03h = eDP, LFP Driven by Int-DisplayPort encoder
+		 */
+		M.x86.R_AX = 0x005f;
+		M.x86.R_CX = 1;
+		break;
+	case 0x5f70:
+		switch (M.x86.R_CH) {
+		case 0:
+			/* Get Mux */
+			printk(BIOS_DEBUG, "Get Mux\n");
+			M.x86.R_AX = 0x005f;
+			M.x86.R_CL = 0;
+			break;
+		case 1:
+			printk(BIOS_DEBUG, "Set Mux\n");
+			/* Set Mux */
+			M.x86.R_AX = 0x005f;
+			M.x86.R_CX = 0;
+			break;
+		case 2:
+			printk(BIOS_DEBUG, "Get SG Mode\n");
+			/* Get SG/Non-SG mode */
+			M.x86.R_AX = 0x005f;
+			M.x86.R_CX = 0;
+			break;
+		default:
+			/* Interrupt was not handled */
+			printk(BIOS_DEBUG, "Unknown INT15 5f70 function: 0x%02x\n",
+				M.x86.R_CH);
+			return 0;
+		}
+		break;
+	default:
+		/* Interrupt was not handled */
+		printk(BIOS_DEBUG, "Unknown INT15 function: 0x%04x\n",
+			M.x86.R_AX);
+		return 0;
+	}
+
+	/* Interrupt handled */
+	return 1;
+}
+#endif
+
+#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE
+static void int15_install(void)
+{
+#if CONFIG_PCI_OPTION_ROM_RUN_YABEL
+	typedef int (* yabel_handleIntFunc)(void);
+	extern yabel_handleIntFunc yabel_intFuncArray[256];
+	yabel_intFuncArray[0x15] = int15_handler;
+#endif
+#ifdef CONFIG_PCI_OPTION_ROM_RUN_REALMODE
+	mainboard_interrupt_handlers(0x15, &int15_handler);
+#endif
+}
+#endif
+
+/* Audio Setup */
+
+extern const u32 * cim_verb_data;
+extern u32 cim_verb_data_size;
+
+static void verb_setup(void)
+{
+	cim_verb_data = mainboard_cim_verb_data;
+	cim_verb_data_size = sizeof(mainboard_cim_verb_data);
+}
+
+static void mainboard_init(device_t dev)
+{
+	/* Initialize the Embedded Controller */
+	lumpy_ec_init();
+}
+
+// mainboard_enable is executed as first thing after
+// enumerate_buses().
+
+static void mainboard_enable(device_t dev)
+{
+	dev->ops->init = mainboard_init;
+#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE
+	/* Install custom int15 handler for VGA OPROM */
+	int15_install();
+#endif
+	verb_setup();
+}
+
+static int lumpy_smbios_type41_irq(int *handle, unsigned long *current,
+				   const char *name, u8 irq, u8 addr)
+{
+	struct smbios_type41 *t = (struct smbios_type41 *)*current;
+	int len = sizeof(struct smbios_type41);
+
+	memset(t, 0, sizeof(struct smbios_type41));
+	t->type = SMBIOS_ONBOARD_DEVICES_EXTENDED_INFORMATION;
+	t->handle = *handle;
+	t->length = len - 2;
+	t->reference_designation = smbios_add_string(t->eos, name);
+	t->device_type = SMBIOS_DEVICE_TYPE_OTHER;
+	t->device_status = 1;
+	t->device_type_instance = irq;
+	t->segment_group_number = 0;
+	t->bus_number = addr;
+	t->function_number = 0;
+	t->device_number = 0;
+
+	len = t->length + smbios_string_table_len(t->eos);
+	*current += len;
+	*handle += 1;
+	return len;
+}
+
+
+static int lumpy_onboard_smbios_data(device_t dev, int *handle,
+				     unsigned long *current)
+{
+	int len = 0;
+
+	len += lumpy_smbios_type41_irq(handle, current,
+				       LUMPY_LIGHTSENSOR_NAME,
+				       LUMPY_LIGHTSENSOR_IRQ,
+				       LUMPY_LIGHTSENSOR_I2C_ADDR);
+
+	len += lumpy_smbios_type41_irq(handle, current,
+				       LUMPY_TRACKPAD_NAME,
+				       LUMPY_TRACKPAD_IRQ,
+				       LUMPY_TRACKPAD_I2C_ADDR);
+
+	return len;
+}
+
+struct chip_operations mainboard_ops = {
+	CHIP_NAME("Samsung Lumpy ChromeBook")
+	.enable_dev = mainboard_enable,
+	.get_smbios_data = lumpy_onboard_smbios_data,
+};
+
diff --git a/src/mainboard/samsung/lumpy/mainboard_smi.c b/src/mainboard/samsung/lumpy/mainboard_smi.c
new file mode 100644
index 0000000000..2d396b03b8
--- /dev/null
+++ b/src/mainboard/samsung/lumpy/mainboard_smi.c
@@ -0,0 +1,129 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <console/console.h>
+#include <cpu/x86/smm.h>
+#include <southbridge/intel/bd82x6x/nvs.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/bd82x6x/me.h>
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <cpu/intel/model_206ax/model_206ax.h>
+#include <ec/smsc/mec1308/ec.h>
+#include "ec.h"
+
+/* The southbridge SMI handler checks whether gnvs has a
+ * valid pointer before calling the trap handler
+ */
+extern global_nvs_t *gnvs;
+
+int mainboard_io_trap_handler(int smif)
+{
+	switch (smif) {
+	case 0x99:
+		printk(BIOS_DEBUG, "Sample\n");
+		gnvs->smif = 0;
+		break;
+	default:
+		return 0;
+	}
+
+	/* On success, the IO Trap Handler returns 0
+	 * On failure, the IO Trap Handler returns a value != 0
+	 *
+	 * For now, we force the return value to 0 and log all traps to
+	 * see what's going on.
+	 */
+	//gnvs->smif = 0;
+	return 1;
+}
+
+static u8 mainboard_smi_ec(void)
+{
+	u8 cmd;
+	u32 pm1_cnt;
+	extern u16 pmbase; /* Set in southbridge SMI handler */
+
+	cmd = read_ec_command_byte(EC_GET_SMI_CAUSE);
+
+	switch (cmd) {
+	case EC_LID_CLOSE:
+		printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n");
+
+		/* Go to S5 */
+		pm1_cnt = inl(pmbase + PM1_CNT);
+		pm1_cnt |= (0xf << 10);
+		outl(pm1_cnt, pmbase + PM1_CNT);
+		break;
+	}
+
+	return cmd;
+}
+
+void mainboard_smi_gpi(u16 gpi_sts)
+{
+	if (gpi_sts & (1 << EC_SMI_GPI)) {
+		/* Process all pending EC requests */
+		ec_set_ports(EC_MAILBOX_PORT, EC_MAILBOX_PORT+1);
+		while (mainboard_smi_ec() != 0xff);
+
+		/* The EC may keep asserting SMI# for some
+		 * period unless we kick it here.
+		 */
+		send_ec_command(EC_SMI_DISABLE);
+		send_ec_command(EC_SMI_ENABLE);
+	}
+}
+
+#define APMC_FINALIZE 0xcb
+
+static int mainboard_finalized = 0;
+
+int mainboard_smi_apmc(u8 apmc)
+{
+	ec_set_ports(EC_MAILBOX_PORT, EC_MAILBOX_PORT+1);
+
+	switch (apmc) {
+	case 0xe1: /* ACPI ENABLE */
+		send_ec_command(EC_SMI_DISABLE);
+		send_ec_command(EC_ACPI_ENABLE);
+		break;
+
+	case 0x1e: /* ACPI DISABLE */
+		send_ec_command(EC_SMI_ENABLE);
+		send_ec_command(EC_ACPI_DISABLE);
+		break;
+
+	case APMC_FINALIZE:
+		if (mainboard_finalized) {
+			printk(BIOS_DEBUG, "SMI#: Already finalized\n");
+			return 0;
+		}
+
+		intel_me_finalize_smm();
+		intel_pch_finalize_smm();
+		intel_sandybridge_finalize_smm();
+		intel_model_206ax_finalize_smm();
+
+		mainboard_finalized = 1;
+		break;
+	}
+	return 0;
+}
diff --git a/src/mainboard/samsung/lumpy/onboard.h b/src/mainboard/samsung/lumpy/onboard.h
new file mode 100644
index 0000000000..6bdf057eaa
--- /dev/null
+++ b/src/mainboard/samsung/lumpy/onboard.h
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef LUMPY_ONBOARD_H
+#define LUMPY_ONBOARD_H
+
+#include <arch/smp/mpspec.h>
+
+#define LUMPY_LIGHTSENSOR_NAME      "lightsensor"
+#define LUMPY_LIGHTSENSOR_I2C_ADDR  0x44
+#define LUMPY_LIGHTSENSOR_IRQ       20
+
+#define LUMPY_TRACKPAD_NAME         "trackpad"
+#define LUMPY_TRACKPAD_I2C_ADDR     0x67
+#define LUMPY_TRACKPAD_IRQ          21
+
+#endif
diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c
new file mode 100644
index 0000000000..7aa4746948
--- /dev/null
+++ b/src/mainboard/samsung/lumpy/romstage.c
@@ -0,0 +1,387 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2010 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <lib.h>
+#include <timestamp.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <device/pci_def.h>
+#include <device/pnp_def.h>
+#include <cpu/x86/lapic.h>
+#include <pc80/mc146818rtc.h>
+#include <cbfs.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include "northbridge/intel/sandybridge/sandybridge.h"
+#include "northbridge/intel/sandybridge/raminit.h"
+#include "southbridge/intel/bd82x6x/pch.h"
+#include "southbridge/intel/bd82x6x/gpio.h"
+#include <arch/cpu.h>
+#include <cpu/x86/bist.h>
+#include <cpu/x86/msr.h>
+#include "option_table.h"
+#include "gpio.h"
+#if CONFIG_CONSOLE_SERIAL8250
+#include "superio/smsc/lpc47n207/lpc47n207.h"
+#include "superio/smsc/lpc47n207/early_serial.c"
+#endif
+#if CONFIG_CHROMEOS
+#include <vendorcode/google/chromeos/chromeos.h>
+#endif
+
+static void pch_enable_lpc(void)
+{
+	/* Set COM1/COM2 decode range */
+	pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010);
+
+#if CONFIG_CONSOLE_SERIAL8250
+	/* Enable SuperIO + EC + KBC + COM1 + lpc47n207 config*/
+	pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN |
+		KBC_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN);
+
+	/* map full 256 bytes at 0x1600 to the LPC bus */
+	pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0xfc1601);
+
+	try_enabling_LPC47N207_uart();
+#else
+	/* Enable SuperIO + EC + KBC */
+	pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN |
+		KBC_LPC_EN);
+#endif
+}
+
+static void rcba_config(void)
+{
+	u32 reg32;
+
+	/*
+	 *             GFX    INTA -> PIRQA (MSI)
+	 * D28IP_P1IP  WLAN   INTA -> PIRQB
+	 * D28IP_P4IP  ETH0   INTB -> PIRQC (MSI)
+	 * D29IP_E1P   EHCI1  INTA -> PIRQD
+	 * D26IP_E2P   EHCI2  INTA -> PIRQB
+	 * D31IP_SIP   SATA   INTA -> PIRQA (MSI)
+	 * D31IP_SMIP  SMBUS  INTC -> PIRQH
+	 * D31IP_TTIP  THRT   INTB -> PIRQG
+	 * D27IP_ZIP   HDA    INTA -> PIRQG (MSI)
+	 *
+	 * LIGHTSENSOR             -> PIRQE (Edge Triggered)
+	 * TRACKPAD                -> PIRQF (Edge Triggered)
+	 */
+
+	/* Device interrupt pin register (board specific) */
+	RCBA32(D31IP) = (INTB << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
+		(INTC << D31IP_SMIP) | (INTA << D31IP_SIP);
+	RCBA32(D30IP) = (NOINT << D30IP_PIP);
+	RCBA32(D29IP) = (INTA << D29IP_E1P);
+	RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) |
+		(INTB << D28IP_P4IP);
+	RCBA32(D27IP) = (INTA << D27IP_ZIP);
+	RCBA32(D26IP) = (INTA << D26IP_E2P);
+	RCBA32(D25IP) = (NOINT << D25IP_LIP);
+	RCBA32(D22IP) = (NOINT << D22IP_MEI1IP);
+
+	/* Device interrupt route registers */
+	DIR_ROUTE(D31IR, PIRQA, PIRQG, PIRQH, PIRQB);
+	DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQG, PIRQH);
+	DIR_ROUTE(D28IR, PIRQB, PIRQC, PIRQD, PIRQE);
+	DIR_ROUTE(D27IR, PIRQG, PIRQH, PIRQA, PIRQB);
+	DIR_ROUTE(D26IR, PIRQB, PIRQC, PIRQD, PIRQA);
+	DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);
+	DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
+
+	/* Enable IOAPIC (generic) */
+	RCBA16(OIC) = 0x0100;
+	/* PCH BWG says to read back the IOAPIC enable register */
+	(void) RCBA16(OIC);
+
+	/* Enable upper 128bytes of CMOS (generic) */
+	RCBA32(RC) = (1 << 2);
+
+	/* Disable unused devices (board specific) */
+	reg32 = RCBA32(FD);
+	reg32 |= PCH_DISABLE_ALWAYS;
+	RCBA32(FD) = reg32;
+}
+
+static void early_pch_init(void)
+{
+	u8 reg8;
+
+	// reset rtc power status
+	reg8 = pci_read_config8(PCH_LPC_DEV, 0xa4);
+	reg8 &= ~(1 << 2);
+	pci_write_config8(PCH_LPC_DEV, 0xa4, reg8);
+}
+
+void main(unsigned long bist)
+{
+	int boot_mode = 0;
+	int cbmem_was_initted;
+	u32 pm1_cnt;
+	u16 pm1_sts;
+
+#if CONFIG_COLLECT_TIMESTAMPS
+	tsc_t start_romstage_time;
+	tsc_t before_dram_time;
+	tsc_t after_dram_time;
+	tsc_t base_time = {
+		.lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc),
+		.hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0)
+	};
+#endif
+
+	struct pei_data pei_data = {
+		.mchbar = 0xfed10000,
+		.dmibar = 0xfed18000,
+		.epbar = 0xfed19000,
+		.pciexbar = 0xf0000000,
+		.smbusbar = 0x400,
+		.wdbbar = 0x4000000,
+		.wdbsize = 0x1000,
+		.hpet_address = 0xfed00000,
+		.rcba = 0xfed1c000,
+		.pmbase = 0x500,
+		.gpiobase = 0x480,
+		.thermalbase = 0xfed08000,
+		.system_type = 0, // 0 Mobile, 1 Desktop/Server
+		.tseg_size = CONFIG_SMM_TSEG_SIZE,
+		.spd_addresses = { 0x50, 0x00,0xf0,0x00 },
+		.ts_addresses = { 0x30, 0x00, 0x00, 0x00 },
+		.ec_present = 1,
+		// 0 = leave channel enabled
+		// 1 = disable dimm 0 on channel
+		// 2 = disable dimm 1 on channel
+		// 3 = disable dimm 0+1 on channel
+		.dimm_channel0_disabled = 2,
+		.dimm_channel1_disabled = 2,
+		.usb_port_config = {
+			{ 1, 0, 0x0080 }, /* P0: Port 0      (OC0) */
+			{ 1, 1, 0x0080 }, /* P1: Port 1      (OC1) */
+			{ 1, 0, 0x0040 }, /* P2: MINIPCIE1   (no OC) */
+			{ 1, 0, 0x0040 }, /* P3: MMC         (no OC) */
+			{ 0, 0, 0x0000 }, /* P4: Empty */
+			{ 0, 0, 0x0000 }, /* P5: Empty */
+			{ 0, 0, 0x0000 }, /* P6: Empty */
+			{ 0, 0, 0x0000 }, /* P7: Empty */
+			{ 1, 4, 0x0040 }, /* P8: MINIPCIE2   (no OC) */
+			{ 0, 4, 0x0000 }, /* P9: Empty */
+			{ 0, 4, 0x0000 }, /* P10: Empty */
+			{ 1, 4, 0x0040 }, /* P11: Camera     (no OC) */
+			{ 0, 4, 0x0000 }, /* P12: Empty */
+			{ 0, 4, 0x0000 }, /* P13: Empty */
+		},
+		.spd_data = {
+		}
+	};
+
+	typedef const uint8_t spd_blob[256];
+	struct cbfs_file *spd_file;
+	spd_blob *spd_data;
+
+
+#if CONFIG_COLLECT_TIMESTAMPS
+	start_romstage_time = rdtsc();
+#endif
+
+	if (bist == 0)
+		enable_lapic();
+
+	pch_enable_lpc();
+
+	/* Enable GPIOs */
+	pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1);
+	pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10);
+	setup_pch_gpios(&lumpy_gpio_map);
+
+	console_init();
+
+#if CONFIG_CHROMEOS
+	save_chromeos_gpios();
+#endif
+
+	/* Halt if there was a built in self test failure */
+	report_bist_failure(bist);
+
+	if (MCHBAR16(SSKPD) == 0xCAFE) {
+		printk(BIOS_DEBUG, "soft reset detected\n");
+		boot_mode = 1;
+
+		/* System is not happy after keyboard reset... */
+		printk(BIOS_DEBUG, "Issuing CF9 warm reset\n");
+		outb(0x6, 0xcf9);
+		hlt();
+	}
+
+	/* Perform some early chipset initialization required
+	 * before RAM initialization can work
+	 */
+	sandybridge_early_initialization(SANDYBRIDGE_MOBILE);
+	printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n");
+
+	/* Check PM1_STS[15] to see if we are waking from Sx */
+	pm1_sts = inw(DEFAULT_PMBASE + PM1_STS);
+
+	/* Read PM1_CNT[12:10] to determine which Sx state */
+	pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT);
+
+	if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) {
+#if CONFIG_HAVE_ACPI_RESUME
+		printk(BIOS_DEBUG, "Resume from S3 detected.\n");
+		boot_mode = 2;
+		/* Clear SLP_TYPE. This will break stage2 but
+		 * we care for that when we get there.
+		 */
+		outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT);
+#else
+		printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
+#endif
+	}
+
+	post_code(0x38);
+	/* Enable SPD ROMs and DDR-III DRAM */
+	enable_smbus();
+
+	/* Prepare USB controller early in S3 resume */
+	if (boot_mode == 2)
+		enable_usb_bar();
+
+	u32 gp_lvl2 = inl(DEFAULT_GPIOBASE + 0x38);
+	u8 gpio33, gpio41, gpio49;
+	gpio33 = (gp_lvl2 >> (33-32)) & 1;
+	gpio41 = (gp_lvl2 >> (41-32)) & 1;
+	gpio49 = (gp_lvl2 >> (49-32)) & 1;
+	printk(BIOS_DEBUG, "Memory Straps:\n");
+	printk(BIOS_DEBUG, " - memory capacity %dGB\n",
+		gpio33 ? 2 : 1);
+	printk(BIOS_DEBUG, " - die revision %d\n",
+		gpio41 ? 2 : 1);
+	printk(BIOS_DEBUG, " - vendor %s\n",
+		gpio49 ? "Samsung" : "Other");
+
+	int spd_index = 0;
+
+	switch ((gpio49 << 2) | (gpio41 << 1) | gpio33) {
+	case 0: // Other 1G Rev 1
+		spd_index = 0;
+		break;
+	case 2: // Other 1G Rev 2
+		spd_index = 1;
+		break;
+	case 1: // Other 2G Rev 1
+	case 3: // Other 2G Rev 2
+		spd_index = 2;
+		break;
+	case 4: // Samsung 1G Rev 1
+		spd_index = 3;
+		break;
+	case 6: // Samsung 1G Rev 2
+		spd_index = 4;
+		break;
+	case 5: // Samsung 2G Rev 1
+	case 7: // Samsung 2G Rev 2
+		spd_index = 5;
+		break;
+	}
+
+	spd_file = cbfs_find("spd.bin");
+	if (!spd_file)
+		die("SPD data not found.");
+	if (spd_file->len < (spd_index + 1) * 256)
+		die("Missing SPD data.");
+	spd_data = (spd_blob *)CBFS_SUBHEADER(spd_file);
+	// leave onboard dimm address at f0, and copy spd data there.
+	memcpy(pei_data.spd_data[0], spd_data[spd_index], 256);
+
+	post_code(0x39);
+	pei_data.boot_mode = boot_mode;
+#if CONFIG_COLLECT_TIMESTAMPS
+	before_dram_time = rdtsc();
+#endif
+	sdram_initialize(&pei_data);
+
+#if CONFIG_COLLECT_TIMESTAMPS
+	after_dram_time = rdtsc();
+#endif
+	post_code(0x3a);
+	/* Perform some initialization that must run before stage2 */
+	early_pch_init();
+	post_code(0x3b);
+
+	rcba_config();
+	post_code(0x3c);
+
+	/* Initialize the internal PCIe links before we go into stage2 */
+	sandybridge_late_initialization();
+
+	post_code(0x3e);
+	quick_ram_check();
+
+	MCHBAR16(SSKPD) = 0xCAFE;
+
+#if CONFIG_EARLY_CBMEM_INIT
+	cbmem_was_initted = !cbmem_initialize();
+#else
+	cbmem_was_initted = cbmem_reinit((uint64_t) (get_top_of_ram()
+						     - HIGH_MEMORY_SIZE));
+#endif
+
+#if CONFIG_HAVE_ACPI_RESUME
+	/* If there is no high memory area, we didn't boot before, so
+	 * this is not a resume. In that case we just create the cbmem toc.
+	 */
+
+	*(u32 *)CBMEM_BOOT_MODE = 0;
+	*(u32 *)CBMEM_RESUME_BACKUP = 0;
+
+	if ((boot_mode == 2) && cbmem_was_initted) {
+		void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
+		if (resume_backup_memory) {
+			*(u32 *)CBMEM_BOOT_MODE = boot_mode;
+			*(u32 *)CBMEM_RESUME_BACKUP = (u32)resume_backup_memory;
+		}
+		/* Magic for S3 resume */
+		pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d);
+	} else if (boot_mode == 2) {
+		/* Failed S3 resume, reset to come up cleanly */
+		outb(0x6, 0xcf9);
+		hlt();
+	} else {
+		pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe);
+	}
+#endif
+	post_code(0x3f);
+#if CONFIG_CHROMEOS
+	init_chromeos(boot_mode);
+#endif
+#if CONFIG_COLLECT_TIMESTAMPS
+	timestamp_init(base_time);
+	timestamp_add(TS_START_ROMSTAGE, start_romstage_time );
+	timestamp_add(TS_BEFORE_INITRAM, before_dram_time );
+	timestamp_add(TS_AFTER_INITRAM, after_dram_time );
+	timestamp_add_now(TS_END_ROMSTAGE);
+#endif
+#if CONFIG_CONSOLE_CBMEM
+	/* Keep this the last thing this function does. */
+	cbmemc_reinit();
+#endif
+}
diff --git a/src/mainboard/samsung/lumpy/spd.hex b/src/mainboard/samsung/lumpy/spd.hex
new file mode 100644
index 0000000000..8690886207
--- /dev/null
+++ b/src/mainboard/samsung/lumpy/spd.hex
@@ -0,0 +1,96 @@
+0000000: 92 10 0b 03 02 11 00 01 03 52 01 08 0c 00 3e 00  .........R....>.
+0000010: 69 78 69 30 69 11 20 89 70 03 3c 3c 00 f0 83 01  ixi0i. .p.<<....
+0000020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+0000030: 00 00 00 00 00 00 00 00 00 00 00 00 0f 11 21 00  ..............!.
+0000040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+0000050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+0000060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+0000070: 00 00 00 00 00 80 ce 01 00 00 00 00 00 00 d3 0d  ................
+0000080: 4d 34 37 31 42 32 38 37 33 46 48 53 2d 43 48 39  M471B2873FHS-CH9
+0000090: 20 20 00 00 80 ce 00 00 00 00 00 00 00 00 00 00    ..............
+00000a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+00000b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+00000c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+00000d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+00000e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+00000f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+0000100: 92 10 0b 03 02 11 00 01 03 52 01 08 0f 00 1e 00  .........R......
+0000110: 69 78 69 3c 69 11 2c 95 70 03 3c 3c 01 2c 83 01  ixi<i.,.p.<<.,..
+0000120: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+0000130: 00 00 00 00 00 00 00 00 00 00 00 00 0f 11 21 00  ..............!.
+0000140: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+0000150: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+0000160: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+0000170: 00 00 00 00 00 80 ce 02 10 31 81 1d 77 ce 91 a4  .........1..w...
+0000180: 4d 34 37 31 42 32 38 37 33 46 48 53 2d 43 46 38  M471B2873FHS-CF8
+0000190: 20 20 00 00 80 ce 00 00 00 53 47 30 44 35 31 31    .......SG0D511
+00001a0: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+00001b0: 01 a0 04 38 20 06 57 31 00 00 00 00 00 00 00 00  ...8 .W1........
+00001c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+00001d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+00001e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+00001f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+0000200: 92 10 0b 03 03 19 00 01 03 52 01 08 0c 00 7e 00  .........R....~.
+0000210: 69 78 69 30 69 11 20 89 00 05 3c 3c 00 f0 83 81  ixi0i. ...<<....
+0000220: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+0000230: 00 00 00 00 00 00 00 00 00 00 00 00 0f 11 41 00  ..............A.
+0000240: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+0000250: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+0000260: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+0000270: 00 00 00 00 00 02 fe 00 00 00 00 00 00 00 29 2b  ..............)+
+0000280: 45 42 4a 32 30 55 46 38 42 44 55 30 2d 44 4a 2d  EBJ20UF8BDU0-DJ-
+0000290: 46 20 30 20 02 fe 00 00 00 00 00 00 00 00 00 00  F 0 ............
+00002a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+00002b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+00002c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+00002d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+00002e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+00002f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+0000300: 92 11 0b 03 02 11 00 01 03 11 01 08 0c 00 3e 00  ..............>.
+0000310: 69 78 69 30 69 11 20 89 70 03 3c 3c 00 f0 83 01  ixi0i. .p.<<....
+0000320: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+0000330: 00 00 00 00 00 00 00 00 00 00 00 00 0f 11 41 00  ..............A.
+0000340: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+0000350: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+0000360: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+0000370: 00 00 00 00 00 80 ce 01 00 00 00 00 00 00 cf 74  ...............t
+0000380: 4d 34 37 31 42 32 38 37 33 47 42 30 2d 43 48 39  M471B2873GB0-CH9
+0000390: 20 20 00 00 80 ce 00 00 00 00 00 00 00 00 00 00    ..............
+00003a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+00003b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+00003c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+00003d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+00003e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+00003f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+0000400: 92 11 0b 03 02 11 00 01 03 11 01 08 0f 00 1e 00  ................
+0000410: 69 78 69 3c 69 11 2c 95 70 03 3c 3c 01 2c 83 01  ixi<i.,.p.<<.,..
+0000420: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+0000430: 00 00 00 00 00 00 00 00 00 00 00 00 0f 11 41 00  ..............A.
+0000440: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+0000450: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+0000460: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+0000470: 00 00 00 00 00 80 ce 01 00 00 00 00 00 00 8d dd  ................
+0000480: 4d 34 37 31 42 32 38 37 33 47 42 30 2d 43 46 38  M471B2873GB0-CF8
+0000490: 20 20 00 00 80 ce 00 00 00 00 00 00 00 00 00 00    ..............
+00004a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+00004b0: 01 a0 04 38 20 06 57 31 00 00 00 00 00 00 00 00  ...8 .W1........
+00004c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+00004d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+00004e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+00004f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+0000500: 92 10 0b 03 03 19 00 01 03 52 01 08 0c 00 3e 00  .........R....>.
+0000510: 69 78 69 30 69 11 20 89 00 05 3c 3c 00 f0 83 01  ixi0i. ...<<....
+0000520: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+0000530: 00 00 00 00 00 00 00 00 00 00 00 00 0f 11 21 00  ..............!.
+0000540: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+0000550: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+0000560: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+0000570: 00 00 00 00 00 80 ce 01 00 00 00 00 00 00 4c db  ..............L.
+0000580: 4d 34 37 31 42 35 37 37 33 43 48 53 2d 43 48 39  M471B5773CHS-CH9
+0000590: 20 20 00 00 80 ce 00 00 00 53 30 58 44 30 30 30    .......S0XD000
+00005a0: 01 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+00005b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+00005c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+00005d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+00005e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+00005f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
diff --git a/src/mainboard/samsung/lumpy/thermal.h b/src/mainboard/samsung/lumpy/thermal.h
new file mode 100644
index 0000000000..82c413cc68
--- /dev/null
+++ b/src/mainboard/samsung/lumpy/thermal.h
@@ -0,0 +1,52 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef LUMPY_THERMAL_H
+#define LUMPY_THERMAL_H
+
+/* Fan is OFF */
+#define FAN4_THRESHOLD_OFF	0
+#define FAN4_THRESHOLD_ON	0
+
+/* Fan is at LOW speed */
+#define FAN3_THRESHOLD_OFF	44
+#define FAN3_THRESHOLD_ON	48
+
+/* Fan is at MEDIUM speed */
+#define FAN2_THRESHOLD_OFF	48
+#define FAN2_THRESHOLD_ON	54
+
+/* Fan is at HIGH speed */
+#define FAN1_THRESHOLD_OFF	60
+#define FAN1_THRESHOLD_ON	64
+
+/* Fan is at FULL speed */
+#define FAN0_THRESHOLD_OFF	66
+#define FAN0_THRESHOLD_ON	78
+
+/* Temperature which OS will shutdown at */
+#define CRITICAL_TEMPERATURE	100
+
+/* Temperature which OS will throttle CPU */
+#define PASSIVE_TEMPERATURE	90
+
+/* Tj_max value for calculating PECI CPU temperature */
+#define MAX_TEMPERATURE		100
+
+#endif
author	Stefan Reinauer <stefan.reinauer@coreboot.org>	2012-04-27 23:19:58 +0200
committer	Stefan Reinauer <stefan.reinauer@coreboot.org>	2012-04-30 23:09:10 +0200
commit	155e9b5533131f4b944ebb7e5714a871a1294dda (patch)
tree	6d3cbc7a1442648560f94675a34268bbe1671e17 /src/mainboard/samsung/lumpy
parent	6651da3bcd51ad6ea918c21564eb505b76c8c7aa (diff)
download	coreboot-155e9b5533131f4b944ebb7e5714a871a1294dda.tar.xz