diff options
author | Joel Kitching <kitching@google.com> | 2019-03-23 12:41:04 +0800 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2019-03-27 08:21:01 +0000 |
commit | 2e1f65545f7ee826322aef6a586a2580a23db775 (patch) | |
tree | 9bb929c38b2b738a5fa4f517f185f7be9ff08304 /src/mainboard/samsung/stumpy/chromeos.c | |
parent | f7f41a663f11f57a463177d4f7c9df165830c821 (diff) | |
download | coreboot-2e1f65545f7ee826322aef6a586a2580a23db775.tar.xz |
chromeos: update old boards to use lb_add_gpios notation
Instead of manually filling out the lb_gpios struct,
use the newer lb_add_gpios notation, which is more
compact and less error-prone.
BUG=b:124141368
TEST=util/lint/checkpatch.pl -g origin/master..HEAD
TEST=util/abuild/abuild -B -e -y -c 50 -p none -x
BRANCH=none
Change-Id: I90795f32be5de881c94519933f36127098c184df
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32031
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/samsung/stumpy/chromeos.c')
-rw-r--r-- | src/mainboard/samsung/stumpy/chromeos.c | 55 |
1 files changed, 20 insertions, 35 deletions
diff --git a/src/mainboard/samsung/stumpy/chromeos.c b/src/mainboard/samsung/stumpy/chromeos.c index 295c31f49d..b1ad137113 100644 --- a/src/mainboard/samsung/stumpy/chromeos.c +++ b/src/mainboard/samsung/stumpy/chromeos.c @@ -31,46 +31,31 @@ #if ENV_RAMSTAGE #include <boot/coreboot_tables.h> -#define GPIO_COUNT 5 - void fill_lb_gpios(struct lb_gpios *gpios) { struct device *dev = pcidev_on_root(0x1f, 0); u16 gen_pmcon_1 = pci_read_config32(dev, GEN_PMCON_1); - gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio)); - gpios->count = GPIO_COUNT; - - /* Write Protect: GPIO68 = CHP3_SPI_WP */ - gpios->gpios[0].port = GPIO_SPI_WP; - gpios->gpios[0].polarity = ACTIVE_HIGH; - gpios->gpios[0].value = get_write_protect_state(); - strncpy((char *)gpios->gpios[0].name,"write protect", - GPIO_MAX_NAME_LENGTH); - - /* Recovery: GPIO42 = CHP3_REC_MODE# */ - gpios->gpios[1].port = GPIO_REC_MODE; - gpios->gpios[1].polarity = ACTIVE_LOW; - gpios->gpios[1].value = !get_recovery_mode_switch(); - strncpy((char *)gpios->gpios[1].name,"recovery", GPIO_MAX_NAME_LENGTH); - - /* Hard code the lid switch GPIO to open. */ - gpios->gpios[2].port = 100; - gpios->gpios[2].polarity = ACTIVE_HIGH; - gpios->gpios[2].value = 1; - strncpy((char *)gpios->gpios[2].name,"lid", GPIO_MAX_NAME_LENGTH); - - /* Power Button */ - gpios->gpios[3].port = 101; - gpios->gpios[3].polarity = ACTIVE_LOW; - gpios->gpios[3].value = (gen_pmcon_1 >> 9) & 1; - strncpy((char *)gpios->gpios[3].name,"power", GPIO_MAX_NAME_LENGTH); - - /* Did we load the VGA Option ROM? */ - gpios->gpios[4].port = -1; /* Indicate that this is a pseudo GPIO */ - gpios->gpios[4].polarity = ACTIVE_HIGH; - gpios->gpios[4].value = gfx_get_init_done(); - strncpy((char *)gpios->gpios[4].name,"oprom", GPIO_MAX_NAME_LENGTH); + struct lb_gpio chromeos_gpios[] = { + /* Write Protect: GPIO68 = CHP3_SPI_WP */ + {GPIO_SPI_WP, ACTIVE_HIGH, get_write_protect_state(), + "write protect"}, + + /* Recovery: GPIO42 = CHP3_REC_MODE# */ + {GPIO_REC_MODE, ACTIVE_LOW, !get_recovery_mode_switch(), + "recovery"}, + + /* Hard code the lid switch GPIO to open. */ + {100, ACTIVE_HIGH, 1, "lid"}, + + /* Power Button */ + {101, ACTIVE_LOW, (gen_pmcon_1 >> 9) & 1, "power"}, + + /* Did we load the VGA Option ROM? */ + /* -1 indicates that this is a pseudo GPIO */ + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } #endif |