diff options
author | Joel Kitching <kitching@google.com> | 2019-03-17 18:07:25 +0800 |
---|---|---|
committer | Julius Werner <jwerner@chromium.org> | 2019-03-27 06:13:27 +0000 |
commit | 51bbdac7d513f5e0763ff68ecac2fcd3db1d53aa (patch) | |
tree | 86b81ca1014b5d975dfdae46256e60efb7d5408b /src/mainboard/samsung/stumpy | |
parent | ed6996f2babb6efd794e45e18f39a09d2996b2b0 (diff) | |
download | coreboot-51bbdac7d513f5e0763ff68ecac2fcd3db1d53aa.tar.xz |
vboot: deprecate physical dev switch
Currently only two devices make use of physical dev switch:
stumpy, lumpy
Deprecate this switch. If these devices are flashed to ToT,
they may still make use of virtual dev switch, activated
via recovery screen.
BUG=b:124141368, b:124192753, chromium:942901
TEST=util/lint/checkpatch.pl -g origin/master..HEAD
TEST=util/abuild/abuild -B -e -y -c 50 -p none -x
TEST=make clean && make test-abuild
BRANCH=none
Change-Id: I87ec0db6148c1727b95475d94e3e3f6e7ec83193
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31943
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/samsung/stumpy')
-rw-r--r-- | src/mainboard/samsung/stumpy/Kconfig | 1 | ||||
-rw-r--r-- | src/mainboard/samsung/stumpy/chromeos.c | 48 |
2 files changed, 13 insertions, 36 deletions
diff --git a/src/mainboard/samsung/stumpy/Kconfig b/src/mainboard/samsung/stumpy/Kconfig index 36e28ffc6c..d17dc6842f 100644 --- a/src/mainboard/samsung/stumpy/Kconfig +++ b/src/mainboard/samsung/stumpy/Kconfig @@ -21,7 +21,6 @@ config BOARD_SPECIFIC_OPTIONS select INTEL_INT15 config VBOOT - select VBOOT_PHYSICAL_DEV_SWITCH select VBOOT_PHYSICAL_REC_SWITCH select VBOOT_VBNV_CMOS diff --git a/src/mainboard/samsung/stumpy/chromeos.c b/src/mainboard/samsung/stumpy/chromeos.c index d0554447d2..295c31f49d 100644 --- a/src/mainboard/samsung/stumpy/chromeos.c +++ b/src/mainboard/samsung/stumpy/chromeos.c @@ -24,16 +24,14 @@ #define GPIO_SPI_WP 68 #define GPIO_REC_MODE 42 -#define GPIO_DEV_MODE 17 #define FLAG_SPI_WP 0 #define FLAG_REC_MODE 1 -#define FLAG_DEV_MODE 2 #if ENV_RAMSTAGE #include <boot/coreboot_tables.h> -#define GPIO_COUNT 6 +#define GPIO_COUNT 5 void fill_lb_gpios(struct lb_gpios *gpios) { @@ -56,29 +54,23 @@ void fill_lb_gpios(struct lb_gpios *gpios) gpios->gpios[1].value = !get_recovery_mode_switch(); strncpy((char *)gpios->gpios[1].name,"recovery", GPIO_MAX_NAME_LENGTH); - /* Developer: GPIO17 = KBC3_DVP_MODE */ - gpios->gpios[2].port = GPIO_DEV_MODE; - gpios->gpios[2].polarity = ACTIVE_HIGH; - gpios->gpios[2].value = get_developer_mode_switch(); - strncpy((char *)gpios->gpios[2].name,"developer", GPIO_MAX_NAME_LENGTH); - /* Hard code the lid switch GPIO to open. */ - gpios->gpios[3].port = 100; - gpios->gpios[3].polarity = ACTIVE_HIGH; - gpios->gpios[3].value = 1; - strncpy((char *)gpios->gpios[3].name,"lid", GPIO_MAX_NAME_LENGTH); + gpios->gpios[2].port = 100; + gpios->gpios[2].polarity = ACTIVE_HIGH; + gpios->gpios[2].value = 1; + strncpy((char *)gpios->gpios[2].name,"lid", GPIO_MAX_NAME_LENGTH); /* Power Button */ - gpios->gpios[4].port = 101; - gpios->gpios[4].polarity = ACTIVE_LOW; - gpios->gpios[4].value = (gen_pmcon_1 >> 9) & 1; - strncpy((char *)gpios->gpios[4].name,"power", GPIO_MAX_NAME_LENGTH); + gpios->gpios[3].port = 101; + gpios->gpios[3].polarity = ACTIVE_LOW; + gpios->gpios[3].value = (gen_pmcon_1 >> 9) & 1; + strncpy((char *)gpios->gpios[3].name,"power", GPIO_MAX_NAME_LENGTH); /* Did we load the VGA Option ROM? */ - gpios->gpios[5].port = -1; /* Indicate that this is a pseudo GPIO */ - gpios->gpios[5].polarity = ACTIVE_HIGH; - gpios->gpios[5].value = gfx_get_init_done(); - strncpy((char *)gpios->gpios[5].name,"oprom", GPIO_MAX_NAME_LENGTH); + gpios->gpios[4].port = -1; /* Indicate that this is a pseudo GPIO */ + gpios->gpios[4].polarity = ACTIVE_HIGH; + gpios->gpios[4].value = gfx_get_init_done(); + strncpy((char *)gpios->gpios[4].name,"oprom", GPIO_MAX_NAME_LENGTH); } #endif @@ -92,16 +84,6 @@ int get_write_protect_state(void) return (pci_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1; } -int get_developer_mode_switch(void) -{ -#ifdef __SIMPLE_DEVICE__ - pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); -#else - struct device *dev = pcidev_on_root(0x1f, 2); -#endif - return (pci_read_config32(dev, SATA_SP) >> FLAG_DEV_MODE) & 1; -} - int get_recovery_mode_switch(void) { #ifdef __SIMPLE_DEVICE__ @@ -127,16 +109,12 @@ void init_bootmode_straps(void) /* Recovery: GPIO42 = CHP3_REC_MODE#, active low */ if (!get_gpio(GPIO_REC_MODE)) flags |= (1 << FLAG_REC_MODE); - /* Developer: GPIO17 = KBC3_DVP_MODE, active high */ - if (get_gpio(GPIO_DEV_MODE)) - flags |= (1 << FLAG_DEV_MODE); pci_write_config32(dev, SATA_SP, flags); } static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME), - CROS_GPIO_DEV_AH(GPIO_DEV_MODE, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), }; |