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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-07-23 19:08:01 +0300
committerPatrick Georgi <pgeorgi@google.com>2019-07-25 16:03:37 +0000
commit17887d08fee6d10bc4ff8758694b88435365e5d7 (patch)
tree03ef6c6afe204dd47c26177974b0c7d6cc60f574 /src/mainboard/samsung/stumpy
parentb14b55daafbd953d04a3bbf9a66bc7fc5ebd277f (diff)
downloadcoreboot-17887d08fee6d10bc4ff8758694b88435365e5d7.tar.xz
mb/*/chromeos.c: Remove some ENV_RAMSTAGE and __SIMPLE_DEVICE__
Use explicit simple PCI config accessors here. Change-Id: Ifa3814fdd7795479ca5fdbfc4deb3fe8db9805f3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34519 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/samsung/stumpy')
-rw-r--r--src/mainboard/samsung/stumpy/chromeos.c27
1 files changed, 6 insertions, 21 deletions
diff --git a/src/mainboard/samsung/stumpy/chromeos.c b/src/mainboard/samsung/stumpy/chromeos.c
index 9ec4218b01..f316b2256f 100644
--- a/src/mainboard/samsung/stumpy/chromeos.c
+++ b/src/mainboard/samsung/stumpy/chromeos.c
@@ -15,6 +15,7 @@
#include <string.h>
#include <bootmode.h>
+#include <boot/coreboot_tables.h>
#include <device/pci_ops.h>
#include <device/device.h>
#include <device/pci.h>
@@ -28,13 +29,10 @@
#define FLAG_SPI_WP 0
#define FLAG_REC_MODE 1
-#if ENV_RAMSTAGE
-#include <boot/coreboot_tables.h>
-
void fill_lb_gpios(struct lb_gpios *gpios)
{
- struct device *dev = pcidev_on_root(0x1f, 0);
- u16 gen_pmcon_1 = pci_read_config32(dev, GEN_PMCON_1);
+ pci_devfn_t dev = PCI_DEV(0, 0x1f, 0);
+ u16 gen_pmcon_1 = pci_s_read_config32(dev, GEN_PMCON_1);
struct lb_gpio chromeos_gpios[] = {
/* Write Protect: GPIO68 = CHP3_SPI_WP */
@@ -57,36 +55,23 @@ void fill_lb_gpios(struct lb_gpios *gpios)
};
lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
}
-#endif
int get_write_protect_state(void)
{
-#ifdef __SIMPLE_DEVICE__
pci_devfn_t dev = PCI_DEV(0, 0x1f, 2);
-#else
- struct device *dev = pcidev_on_root(0x1f, 2);
-#endif
- return (pci_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1;
+ return (pci_s_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1;
}
int get_recovery_mode_switch(void)
{
-#ifdef __SIMPLE_DEVICE__
pci_devfn_t dev = PCI_DEV(0, 0x1f, 2);
-#else
- struct device *dev = pcidev_on_root(0x1f, 2);
-#endif
- return (pci_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1;
+ return (pci_s_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1;
}
void init_bootmode_straps(void)
{
u32 flags = 0;
-#ifdef __SIMPLE_DEVICE__
pci_devfn_t dev = PCI_DEV(0, 0x1f, 2);
-#else
- struct device *dev = pcidev_on_root(0x1f, 2);
-#endif
/* Write Protect: GPIO68 = CHP3_SPI_WP, active high */
if (get_gpio(GPIO_SPI_WP))
@@ -95,7 +80,7 @@ void init_bootmode_straps(void)
if (!get_gpio(GPIO_REC_MODE))
flags |= (1 << FLAG_REC_MODE);
- pci_write_config32(dev, SATA_SP, flags);
+ pci_s_write_config32(dev, SATA_SP, flags);
}
static const struct cros_gpio cros_gpios[] = {