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| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-01-21 17:55:02 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-01-24 13:39:19 +0000 |
| commit | 7e6946a74c714ff109c35d97001b22c9e868aaea (patch) | |
| tree | 98899e89dc00f8e5504f06d84eb6dc44227b4c80 /src/mainboard/sapphire/pureplatinumh61/devicetree.cb | |
| parent | d6c15d0c8c39015994a180da82c3e6f9538b42de (diff) | |
| download | coreboot-7e6946a74c714ff109c35d97001b22c9e868aaea.tar.xz | |
cpu/intel/model_206ax: Remove the notion of sockets
With the memory controller the separate sockets becomes a useless
distinction. They all used the same code anyway.
UNTESTED: This also updates autoport.
Change-Id: I044d434a5b8fca75db9eb193c7ffc60f3c78212b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/31031
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/sapphire/pureplatinumh61/devicetree.cb')
| -rw-r--r-- | src/mainboard/sapphire/pureplatinumh61/devicetree.cb | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb index f8cd3b2118..95c59dfca3 100644 --- a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb +++ b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb @@ -31,9 +31,6 @@ chip northbridge/intel/sandybridge register "gpu_panel_power_up_delay" = "0" register "gpu_pch_backlight" = "0x00000000" device cpu_cluster 0x0 on - chip cpu/intel/socket_LGA1155 - device lapic 0x0 on end - end chip cpu/intel/model_206ax register "c1_acpower" = "1" register "c1_battery" = "1" @@ -41,6 +38,7 @@ chip northbridge/intel/sandybridge register "c2_battery" = "3" register "c3_acpower" = "5" register "c3_battery" = "5" + device lapic 0x0 on end device lapic 0xacac off end end end |