summaryrefslogtreecommitdiff
path: root/src/mainboard/sapphire/pureplatinumh61/romstage.c
diff options
context:
space:
mode:
authorArthur Heymans <arthur@aheymans.xyz>2019-11-12 19:11:50 +0100
committerPatrick Georgi <pgeorgi@google.com>2019-11-18 11:48:35 +0000
commitfa5d0f835b1f3bb8907e616913cbf7b91d09ef26 (patch)
treeaf8d33b500b91fa9e2f1a76d9115086644ccf3d2 /src/mainboard/sapphire/pureplatinumh61/romstage.c
parent59eb2fdb6b06618311ef118996ca8c1d28a85ffc (diff)
downloadcoreboot-fa5d0f835b1f3bb8907e616913cbf7b91d09ef26.tar.xz
nb/intel/sandybridge: Set up console in bootblock
Change-Id: Ia041b63201b2a4a2fe6ab11e3497c460f88061d1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/mainboard/sapphire/pureplatinumh61/romstage.c')
-rw-r--r--src/mainboard/sapphire/pureplatinumh61/romstage.c59
1 files changed, 0 insertions, 59 deletions
diff --git a/src/mainboard/sapphire/pureplatinumh61/romstage.c b/src/mainboard/sapphire/pureplatinumh61/romstage.c
deleted file mode 100644
index bc08fd8bf2..0000000000
--- a/src/mainboard/sapphire/pureplatinumh61/romstage.c
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2017 Nicola Corna <nicola@corna.info>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <device/pci_ops.h>
-#include <device/pci_def.h>
-#include <northbridge/intel/sandybridge/sandybridge.h>
-#include <northbridge/intel/sandybridge/raminit_native.h>
-#include <southbridge/intel/bd82x6x/pch.h>
-
-void mainboard_pch_lpc_setup(void)
-{
- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x00010000);
-}
-
-void mainboard_late_rcba_config(void)
-{
- /* Disable devices. */
- RCBA32(0x3414) = 0x00000020;
-}
-const struct southbridge_usb_port mainboard_usb_ports[] = {
- { 1, 0, 0 },
- { 1, 0, 0 },
- { 1, 0, 1 },
- { 1, 0, 1 },
- { 1, 0, 2 },
- { 1, 0, 2 },
- { 1, 0, 3 },
- { 1, 0, 3 },
- { 1, 0, 4 },
- { 1, 0, 4 },
- { 1, 0, 6 },
- { 1, 0, 5 },
- { 1, 0, 5 },
- { 1, 0, 6 },
-};
-
-void mainboard_config_superio(void)
-{
-}
-
-void mainboard_get_spd(spd_raw_data *spd, bool id_only)
-{
- read_spd(&spd[0], 0x50, id_only);
- read_spd(&spd[2], 0x51, id_only);
-}