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| author | Angel Pons <th3fanbus@gmail.com> | 2020-11-03 00:29:39 +0100 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-11-23 09:56:20 +0000 |
| commit | c85cce077cc9ded8f33b9b059ce0b165da618639 (patch) | |
| tree | 6911321c436c40374f2ca7a032524e528cec7a32 /src/mainboard/sapphire/pureplatinumh61 | |
| parent | 2c0aa00d6e562b2e6dbe580e188e24ce5e4336e2 (diff) | |
| download | coreboot-c85cce077cc9ded8f33b9b059ce0b165da618639.tar.xz | |
mb/**/cmos.layout: Indent everything with tabs
Time has shown that using spaces never converges into proper alignment.
Change-Id: I5338aeaf139580f9eab3e1e02cb910080a95d2c2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Diffstat (limited to 'src/mainboard/sapphire/pureplatinumh61')
| -rw-r--r-- | src/mainboard/sapphire/pureplatinumh61/cmos.layout | 84 |
1 files changed, 42 insertions, 42 deletions
diff --git a/src/mainboard/sapphire/pureplatinumh61/cmos.layout b/src/mainboard/sapphire/pureplatinumh61/cmos.layout index 62dae3e968..8a45f420d3 100644 --- a/src/mainboard/sapphire/pureplatinumh61/cmos.layout +++ b/src/mainboard/sapphire/pureplatinumh61/cmos.layout @@ -4,71 +4,71 @@ entries # ----------------------------------------------------------------- -0 120 r 0 reserved_memory +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -395 4 e 6 debug_level +395 4 e 6 debug_level -400 8 h 0 volume +400 8 h 0 volume # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail +408 1 e 1 nmi +409 2 e 7 power_on_after_fail -421 1 e 9 sata_mode +421 1 e 9 sata_mode # coreboot config options: cpu -424 1 e 2 hyper_threading +424 1 e 2 hyper_threading # coreboot config options: northbridge -432 3 e 11 gfx_uma_size +432 3 e 11 gfx_uma_size # SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 -960 16 r 0 mrc_scrambler_seed_chk +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -9 0 AHCI -9 1 IDE -11 0 32M -11 1 64M -11 2 96M -11 3 128M -11 4 160M -11 5 192M -11 6 224M +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +9 0 AHCI +9 1 IDE +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M # ----------------------------------------------------------------- checksums |