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authorNicola Corna <nicola@corna.info>2018-04-02 10:27:06 +0200
committerNico Huber <nico.h@gmx.de>2018-05-02 14:14:50 +0000
commite134db253589cff2f8c4cfba171a18c75430aad8 (patch)
tree9713ef34588fcd95f4b94575bf5bc0f0e657ff22 /src/mainboard/sapphire
parentb645ab6f07469c9db40ebd0442e221cbf9c1bfae (diff)
downloadcoreboot-e134db253589cff2f8c4cfba171a18c75430aad8.tar.xz
mb/sapphire/pureplatinumh61: Use custom SPI OPMENU
The SPI chip in this board needs a custom OPMENU, otherwise flashrom fails halfway during the write. From the default OPMENU, Block Erase (0xd8) has been replaced by AAI write (0xad) and Fast Read (0x0b) by Write Disable (0x04). Change-Id: Ie18ee4e32511482dab747c9ffeac60d3994df320 Signed-off-by: Nicola Corna <nicola@corna.info> Reviewed-on: https://review.coreboot.org/25551 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/mainboard/sapphire')
-rw-r--r--src/mainboard/sapphire/pureplatinumh61/devicetree.cb2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb
index 710004f3b5..ed0d997dba 100644
--- a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb
+++ b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb
@@ -59,6 +59,8 @@ chip northbridge/intel/sandybridge
register "pcie_port_coalesce" = "1"
register "sata_interface_speed_support" = "0x3"
register "sata_port_map" = "0x33"
+ register "spi.opprefixes" = "{ 0x50, 0x06 }"
+ register "spi.ops" = "{ { 0, 1, 0x01 }, { 1, 1, 0x02 }, { 1, 0, 0x03 }, { 0, 0, 0x05 }, { 1, 1, 0x20 }, { 0, 0, 0x9f }, { 0, 1, 0xad }, { 0, 1, 0x04 } }"
device pci 16.0 on # Management Engine Interface 1
subsystemid 0x174b 0x1007
end