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| author | Julien Viard de Galbert <jviarddegalbert@online.net> | 2018-02-13 16:55:07 +0100 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-02-16 17:11:55 +0000 |
| commit | bd9ddbcd335c5e7b68c2b78d1bf094459138f941 (patch) | |
| tree | 580162cddd1fa0e6df62d095f2a08ff0b8878f4b /src/mainboard/scaleway/tagada | |
| parent | 4f13640572801323bdcaef408abfed1ec78ee4f0 (diff) | |
| download | coreboot-bd9ddbcd335c5e7b68c2b78d1bf094459138f941.tar.xz | |
mb/scaleway/tagada: Update device tree
Change-Id: I1c42519dbe848b0bbcafa7f923d862ba7c9d8ed5
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/23736
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/scaleway/tagada')
| -rw-r--r-- | src/mainboard/scaleway/tagada/devicetree.cb | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/src/mainboard/scaleway/tagada/devicetree.cb b/src/mainboard/scaleway/tagada/devicetree.cb index 7fce2113b6..acf56a072d 100644 --- a/src/mainboard/scaleway/tagada/devicetree.cb +++ b/src/mainboard/scaleway/tagada/devicetree.cb @@ -53,18 +53,19 @@ chip soc/intel/denverton_ns device pci 04.0 on end # RAS device pci 05.0 on end # RCEC(Root Complex Event Collector) device pci 06.0 on end # Virtual root port 2 (QAT) - device pci 09.0 on end # PCI Express Port 0, cluster #0, x8 - device pci 0e.0 on end # PCI Express Port 4, cluster #1, x4 - device pci 10.0 on end # PCI Express Port 6, cluster #1, x4 + device pci 09.0 on end # PCI Express Port 0, cluster #0, x4 + device pci 10.0 on end # PCI Express Port 6, cluster #1, x2 + device pci 11.0 on end # PCI Express Port 7, cluster #1, x2 device pci 12.0 on end # SMBus Controller 1 + device pci 13.0 on end # SATA Controller 0 device pci 14.0 on end # SATA Controller 1 device pci 15.0 on end # XHCI USB Controller device pci 16.0 on end # Virtual root port 0 (10GBE0) device pci 17.0 on end # Virtual root port 1 (10GBE1) device pci 18.0 on end # CSME HECI 1 device pci 1a.0 on end # UART 0 - device pci 1a.1 on end # UART 1 - device pci 1a.2 on end # UART 2 + device pci 1a.1 off end # UART 1 + device pci 1a.2 off end # UART 2 device pci 1c.0 on end # eMMC device pci 1f.0 on end # LPC bridge device pci 1f.2 on end # PMC/ACPI |