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authorJulien Viard de Galbert <julien@vdg.name>2020-11-11 21:54:28 +0100
committerPatrick Georgi <pgeorgi@google.com>2021-03-19 11:36:27 +0000
commitb3e504c31003fab36329da336a369fdf3a06da09 (patch)
tree3f03c8fb882dcc65562c8fb8b442143c441c8683 /src/mainboard/scaleway
parent7e4ad26b95f79a13d5283509d61c3cfdef9edb77 (diff)
downloadcoreboot-b3e504c31003fab36329da336a369fdf3a06da09.tar.xz
mb/scaleway/tagada: Don't change FIAMUX when Security Override is set
This will not enable M.2 SATA drive if the ME config was lost (For instance after flashing a full flash factory image) This is required so that the system can boot without FIA MUX error during flash update procedure. Change-Id: I55a8bcdc30bc67af2d3e9ccb8844eac599727108 Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/25443 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/scaleway')
-rw-r--r--src/mainboard/scaleway/tagada/hsio.c36
1 files changed, 35 insertions, 1 deletions
diff --git a/src/mainboard/scaleway/tagada/hsio.c b/src/mainboard/scaleway/tagada/hsio.c
index 78599230d7..d305427f02 100644
--- a/src/mainboard/scaleway/tagada/hsio.c
+++ b/src/mainboard/scaleway/tagada/hsio.c
@@ -5,6 +5,8 @@
#include <hsio.h>
#include <gpio_defs.h>
#include <soc/fiamux.h>
+#include <string.h>
+#include <fast_spi_def.h>
#ifdef __RAMSTAGE__
static void update_hsio_info_for_m2_slots(size_t num_of_entry, BL_HSIO_INFORMATION *config)
@@ -12,6 +14,14 @@ static void update_hsio_info_for_m2_slots(size_t num_of_entry, BL_HSIO_INFORMATI
uint32_t reg32;
bool m2a_pcie, m2b_pcie;
uint8_t entry;
+ BL_FIA_MUX_CONFIG_HOB *fiamux_hob_data = get_fiamux_hob_data();
+ uint16_t supported_hsio_lanes;
+ void *spibar = fast_spi_get_bar();
+ uint32_t hsfs;
+
+ /* Configure FIA MUX PCD */
+ supported_hsio_lanes =
+ (uint16_t)fiamux_hob_data->FiaMuxConfig.SkuNumLanesAllowed;
/* Detects modules type */
// _GPIO_4 : LFFF: M2A_CFGn : M2A_SATAn : 0 SATA, 1 PCIe
@@ -29,7 +39,12 @@ static void update_hsio_info_for_m2_slots(size_t num_of_entry, BL_HSIO_INFORMATI
// HSIO default config is for PCIe, only update for SATA
// (also secondary PCIe lines are already set depending on SKU)
for (entry = 0; entry < num_of_entry; entry++) {
- BL_ME_FIA_MUX_CONFIG *mux_config = &(config[entry].FiaConfig.MuxConfiguration);
+ /* only update the active config */
+ if (config[entry].NumLanesSupported != supported_hsio_lanes)
+ continue;
+ BL_ME_FIA_CONFIG *fia_config = &(config[entry].FiaConfig);
+ BL_ME_FIA_MUX_CONFIG *mux_config =
+ &(config[entry].FiaConfig.MuxConfiguration);
BL_ME_FIA_SATA_CONFIG *sata_config =
&(config[entry].FiaConfig.SataLaneConfiguration);
if (!m2a_pcie) {
@@ -46,6 +61,25 @@ static void update_hsio_info_for_m2_slots(size_t num_of_entry, BL_HSIO_INFORMATI
sata_config->BL_MeFiaSataLaneSataSel.Lane12SataSel =
BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED;
}
+
+ /* Check SPIBAR for security override
+ at least one M2 slot is populated with SATA
+ the configuration is different form ME current one */
+ hsfs = read32(spibar + SPIBAR_HSFSTS_CTL);
+ if ((!(hsfs & SPIBAR_HSFSTS_FDOPSS))
+ && (!m2a_pcie || !m2b_pcie)
+ && memcmp(fia_config,
+ &fiamux_hob_data->FiaMuxConfig.FiaMuxConfig,
+ sizeof(BL_ME_FIA_CONFIG))) {
+ /* update configuration to NOT change ME config
+ as it will fail with security override set. */
+ memcpy(fia_config,
+ &fiamux_hob_data->FiaMuxConfig.FiaMuxConfig,
+ sizeof(BL_ME_FIA_CONFIG));
+ printk(BIOS_CRIT, "FLASH SECURITY OVERRIDE SET: "
+ "M2 SATA Slots are not available!\n");
+
+ }
}
}
#endif