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| author | praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com> | 2018-09-21 04:24:16 +0800 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2018-09-21 02:21:40 +0000 |
| commit | 338c8002d2a2d4335b9ebf0e5bcc5b3ca1ce35a4 (patch) | |
| tree | f3cff2a002252f84f8c6aa32ba1c1535621cd700 /src/mainboard/scaleway | |
| parent | c423d7d8f1ecb0de79590f7cd7cb99a6dc0e73d8 (diff) | |
| download | coreboot-338c8002d2a2d4335b9ebf0e5bcc5b3ca1ce35a4.tar.xz | |
soc/intel/cannonlake: Correct ITSS port id.
According to cannon lake PCH BIOS specification document #570374
target port id for interrupt and timer subsystem(ITSS) is C4 instead of C2.
BUG=None
TEST=None
Change-Id: I9f8783c682d2c4c4a86e1c9cf4b9c27a18fdf494
Signed-off-by: praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Reviewed-on: https://review.coreboot.org/28698
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Kin Wai Ng <nelsonaquik@gmail.com>
Diffstat (limited to 'src/mainboard/scaleway')
0 files changed, 0 insertions, 0 deletions