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| author | Furquan Shaikh <furquan@google.com> | 2020-04-21 23:19:52 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2020-04-25 05:56:17 +0000 |
| commit | 8ebbe17b8613c9cf499ab7d5090ed4ee3356c1f9 (patch) | |
| tree | 12c32180f8af59ab1aa4db01a3e53182f86d8f51 /src/mainboard/scaleway | |
| parent | 5d76958de124af3877f9b399a4ec8a6377fe4ffd (diff) | |
| download | coreboot-8ebbe17b8613c9cf499ab7d5090ed4ee3356c1f9.tar.xz | |
soc/intel/tigerlake: Fix FSP SPD index for DDR4
For DDR4, FSP expects channel 0 to set SPD for index 0 and channel 1
to set SPD for index 4. This change adds a helper macro to translate
DDR4 channel # to the index # that the FSP expects.
BUG=b:154445630
TEST=Verified that memory initialization for DDR4 is successful.
Change-Id: I2b6ea2433453a574970c1c33ff629fd54ff5d508
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kane Chen <kane.chen@intel.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Diffstat (limited to 'src/mainboard/scaleway')
0 files changed, 0 insertions, 0 deletions