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author | Mario Scheithauer <mario.scheithauer@siemens.com> | 2017-01-31 15:45:13 +0100 |
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committer | Werner Zeh <werner.zeh@siemens.com> | 2017-02-02 07:06:20 +0100 |
commit | 092db95742fe6e94b391d32d151868f70c5cab84 (patch) | |
tree | 9c5e489af6685aee9f5d2194aa16e3caa0f30361 /src/mainboard/siemens/mc_apl1/dsdt.asl | |
parent | fc18507134bfe2cb9add3f1196832318cd8adcdc (diff) | |
download | coreboot-092db95742fe6e94b391d32d151868f70c5cab84.tar.xz |
siemens/mc_apl1: Add new mainboard
This mainboard is based on Intel's Leafhill CRB with Apollo Lake
silicon. In a first step, it concerns only a copy of intel/leafhill
directory with minimum changes. Special adaptations for MC APL1
mainboard will follow in separate commits.
Change-Id: If0b8a2bc21c99c3be4e6043e8febfb1b91ff0a63
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/18272
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Brenton Dong <brenton.m.dong@intel.com>
Diffstat (limited to 'src/mainboard/siemens/mc_apl1/dsdt.asl')
-rw-r--r-- | src/mainboard/siemens/mc_apl1/dsdt.asl | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/src/mainboard/siemens/mc_apl1/dsdt.asl b/src/mainboard/siemens/mc_apl1/dsdt.asl new file mode 100644 index 0000000000..004523a0ff --- /dev/null +++ b/src/mainboard/siemens/mc_apl1/dsdt.asl @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x05, // DSDT revision: ACPI v5.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20110725 // OEM revision +) +{ + /* global NVS and variables */ + #include <soc/intel/apollolake/acpi/globalnvs.asl> + + /* CPU */ + #include <soc/intel/apollolake/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <soc/intel/apollolake/acpi/northbridge.asl> + #include <soc/intel/apollolake/acpi/southbridge.asl> + #include <soc/intel/apollolake/acpi/pch_hda.asl> + } + } + + /* Chipset specific sleep states */ + #include <soc/intel/apollolake/acpi/sleepstates.asl> +} |