diff options
| author | Mario Scheithauer <mario.scheithauer@siemens.com> | 2019-01-28 16:18:45 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-01-30 11:00:28 +0000 |
| commit | 67be491458198f90803440e41cabe79f58afaae2 (patch) | |
| tree | 79c93814f77798341f5a46964e0c830446f987cb /src/mainboard/siemens/mc_apl1/variants/mc_apl2/gpio.c | |
| parent | 1c105b0c8a4c1910689d9fb5b233e79a2f866c65 (diff) | |
| download | coreboot-67be491458198f90803440e41cabe79f58afaae2.tar.xz | |
siemens/mc_apl2: Activate TPM support
The TPM chip is connected to the SPI interface of APL. The proper chip
select pin needs to be used in order to access the TPM in the memory
mapped space. This needed chip select is internally (inside APL)
routable to GPIO 106. Therefore the change of GPIO 106 mode is needed to
make the TPM work on SPI bus.
TEST=Build coreboot for mc_apl2 board and check the TPM console output.
In addition the TPM was correctly verified by our Linux driver.
Change-Id: I2b0d5a6f2c230187857c2428a70de61f21da6724
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/31125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/mainboard/siemens/mc_apl1/variants/mc_apl2/gpio.c')
| -rw-r--r-- | src/mainboard/siemens/mc_apl1/variants/mc_apl2/gpio.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/gpio.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/gpio.c index a54dae572c..d1ca6793ea 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/gpio.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/gpio.c @@ -363,8 +363,8 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_104, DN_20K, DEEP, NF1, HIZCRx0, ENPD), /* SIO_SPI_FS0_1V8 - Connected to ESPI_CS0# of SMARC connector. */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_105, DN_20K, DEEP, NF1, HIZCRx0, ENPD), - /* SIO_SPI_FS1_1V8 - Connected to ESPI_CS1# of SMARC connector. */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_106, UP_20K, DEEP, NF1, HIZCRx0, ENPD), + /* SIO_SPI_FS1_1V8 - Connected to FST_SPI_CS2_N of SMARC connector. */ + PAD_CFG_NF(GPIO_106, NATIVE, DEEP, NF3), /* SIO_SPI_MISO_1V8 - Connected to ESPI_IO_0 of SMARC connector. */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_109, DN_20K, DEEP, NF1, HIZCRx0, ENPD), /* SIO_SPI_MOSI_1V8 - Connected to ESPI_IO_1 of SMARC connector. */ |