diff options
| author | Mario Scheithauer <mario.scheithauer@siemens.com> | 2019-07-17 10:35:00 +0200 |
|---|---|---|
| committer | Werner Zeh <werner.zeh@siemens.com> | 2019-07-18 11:46:50 +0000 |
| commit | 2c7d1848856ce7bd8539ed4af460a476c39ff2fb (patch) | |
| tree | 1034d2ac269307698ae5548b8f658c4833106173 /src/mainboard/siemens/mc_apl1/variants/mc_apl4 | |
| parent | 7815c074b4689d858fde7c8e02153c40de79645e (diff) | |
| download | coreboot-2c7d1848856ce7bd8539ed4af460a476c39ff2fb.tar.xz | |
mb/siemens/{mc_apl1,...,mc_apl5}: Fix GPIO settings
Correct all GPIOs with reference to the Apollo Lake SoC EDS Vol 4
revision 2.4 chapter 10.1.2.3 List of Pins that are GPIOs but cannot be
used in Function 0 (GPIO) mode.
In additional, set an internal pull to any GPI that does not have an
external resistor so that the input is not in an undefined state.
Change-Id: Ia8fe457eddbed0f4ee6bff9ef9dd7a92545be40b
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34379
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
Diffstat (limited to 'src/mainboard/siemens/mc_apl1/variants/mc_apl4')
| -rw-r--r-- | src/mainboard/siemens/mc_apl1/variants/mc_apl4/gpio.c | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/gpio.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/gpio.c index c7262cad9e..492dae6418 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/gpio.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/gpio.c @@ -178,7 +178,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI(PMC_SPI_CLK, DN_20K, DEEP), /* unused */ /* PMIC Signals unused signals related to an old PMIC interface. */ - PAD_CFG_GPI(PMIC_PWRGOOD, DN_20K, DEEP), /* PMIC_PWRGOOD */ + PAD_CFG_NF(PMIC_PWRGOOD, DN_20K, DEEP, NF1), /* PMIC_PWRGOOD */ PAD_CFG_GPI(PMIC_RESET_B, DN_20K, DEEP), /* PMIC_RESET_B */ PAD_CFG_GPI(GPIO_213, UP_20K, DEEP), /* PMIC_SDWN_B */ PAD_CFG_GPI(GPIO_214, DN_20K, DEEP), /* PMIC_BCUDISW2 */ @@ -318,16 +318,16 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI(GPIO_73, DN_20K, DEEP), /* pin open */ /* no TAP controller pins available on SMARC of APL4 */ - PAD_CFG_GPI(TCK, DN_20K, DEEP), /* pin open */ - PAD_CFG_GPI(TRST_B, DN_20K, DEEP), /* pin open */ - PAD_CFG_GPI(TMS, DN_20K, DEEP), /* pin open */ - PAD_CFG_GPI(TDI, DN_20K, DEEP), /* pin open */ + PAD_CFG_NF(TCK, DN_20K, DEEP, NF1), /* pin open */ + PAD_CFG_NF(TRST_B, DN_20K, DEEP, NF1), /* pin open */ + PAD_CFG_NF(TMS, DN_20K, DEEP, NF1), /* pin open */ + PAD_CFG_NF(TDI, DN_20K, DEEP, NF1), /* pin open */ - PAD_CFG_GPI(CX_PMODE, DN_20K, DEEP), /* pin open */ - PAD_CFG_GPI(CX_PREQ_B, DN_20K, DEEP), /* pin open */ - PAD_CFG_GPI(JTAGX, DN_20K, DEEP), /* pin open */ - PAD_CFG_GPI(CX_PRDY_B, DN_20K, DEEP), /* pin open */ - PAD_CFG_GPI(TDO, DN_20K, DEEP), /* pin open */ + PAD_CFG_NF(CX_PMODE, DN_20K, DEEP, NF1), /* pin open */ + PAD_CFG_NF(CX_PREQ_B, DN_20K, DEEP, NF1), /* pin open */ + PAD_CFG_NF(JTAGX, DN_20K, DEEP, NF1), /* pin open */ + PAD_CFG_NF(CX_PRDY_B, DN_20K, DEEP, NF1), /* pin open */ + PAD_CFG_NF(TDO, DN_20K, DEEP, NF1), /* pin open */ /* GPIO_[216:219] described into EDS Vol1. */ PAD_CFG_GPO(CNV_BRI_DT, 0, DEEP), /* Disable eDP to LVDS bridge */ @@ -335,7 +335,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI(CNV_RGI_DT, DN_20K, DEEP), /* pin open */ /* Writing to following GPIO registers leads to 0xFFFF FFFF in CFG0/1 */ - PAD_CFG_GPI(CNV_RGI_RSP, DN_20K, DEEP), /* pin open */ + PAD_CFG_NF(CNV_RGI_RSP, DN_20K, DEEP, NF1), /* pin open */ /* Serial Voltage Identification */ PAD_CFG_NF(SVID0_ALERT_B, NONE, DEEP, NF1), /* SVID0_ALERT_B */ |