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| author | Mario Scheithauer <mario.scheithauer@siemens.com> | 2019-06-03 16:22:56 +0200 |
|---|---|---|
| committer | Werner Zeh <werner.zeh@siemens.com> | 2019-06-06 10:57:17 +0000 |
| commit | fa36c6c3eed187f3ebc912eede900c8889df481d (patch) | |
| tree | 1416c324647cd6ca11c94cad9cf625fe285fda23 /src/mainboard/siemens/mc_apl1/variants/mc_apl5/Makefile.inc | |
| parent | 5eb81bed2ea503aaf910430da492ed75d27ef94f (diff) | |
| download | coreboot-fa36c6c3eed187f3ebc912eede900c8889df481d.tar.xz | |
siemens/mc_apl5: Add own GPIO table
Because of some differences to the baseboard this board variant needs
its own GPIO table.
Change-Id: Ie3424cb0b867c5d43cd7db9e9ae654196cef5e90
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33172
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src/mainboard/siemens/mc_apl1/variants/mc_apl5/Makefile.inc')
| -rw-r--r-- | src/mainboard/siemens/mc_apl1/variants/mc_apl5/Makefile.inc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Makefile.inc b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Makefile.inc index adf9aff0d4..03759d2633 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Makefile.inc +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Makefile.inc @@ -1,2 +1,5 @@ +romstage-y += gpio.c + +ramstage-y += gpio.c ramstage-y += mainboard.c ramstage-y += ptn3460.c |