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authorWerner Zeh <werner.zeh@siemens.com>2019-05-02 12:45:21 +0200
committerWerner Zeh <werner.zeh@siemens.com>2019-05-06 04:35:08 +0000
commit42065f8f94b910972fb5e7f3f1952a908b94ffc1 (patch)
tree6697ac1b7bb409d26b2d3fc5c29c9dfa043733cb /src/mainboard/siemens/mc_apl1
parent29a1a0857a637651595dc6109dc24243f353cadf (diff)
downloadcoreboot-42065f8f94b910972fb5e7f3f1952a908b94ffc1.tar.xz
mb/siemens/mc_apl2: Limit SD-Card speed to DDR50
Due to PCB limitations the SD-Card interface is not able to operate with the highest frequency reliably. The OS driver will switch to the highest mode if a SD-Card is attached which supports this high frequency mode. In order to work around this PCB limitation disable the high frequency modes in the controller capabilities (SDR104 and HS400 mode) and leave SDR50 and DDR50 enabled. Change-Id: Ia5fed5fb70b027de34170b49620927614a00fb7a Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32542 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/mainboard/siemens/mc_apl1')
-rw-r--r--src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c20
1 files changed, 20 insertions, 0 deletions
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c
index 0c2418ad27..f52091bced 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c
@@ -23,6 +23,11 @@
#include <timer.h>
#include <timestamp.h>
#include <baseboard/variants.h>
+#include <soc/pci_devs.h>
+
+#define SD_CAP_BYP 0x810
+#define SD_CAP_BYP_EN 0x5A
+#define SD_CAP_BYP_REG1 0x814
void variant_mainboard_final(void)
{
@@ -36,6 +41,21 @@ void variant_mainboard_final(void)
cmd |= PCI_COMMAND_MASTER;
pci_write_config16(dev, PCI_COMMAND, cmd);
}
+
+ /* Reduce SD-Card speed to DDR50 because of PCB constraints. */
+ dev = pcidev_path_on_root(PCH_DEVFN_SDCARD);
+ if (dev) {
+ uint32_t reg;
+ struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ if (!res)
+ return;
+
+ write32(res2mmio(res, SD_CAP_BYP, 0), SD_CAP_BYP_EN);
+ reg = read32(res2mmio(res, SD_CAP_BYP_REG1, 0));
+ /* Disable HS400 and SDR104, keep SDR50 and DDR50 modes. */
+ reg &= ~0x20005800;
+ write32(res2mmio(res, SD_CAP_BYP_REG1, 0), reg);
+ }
}
static void wait_for_legacy_dev(void *unused)