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| author | Mario Scheithauer <mario.scheithauer@siemens.com> | 2018-08-23 12:01:12 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-08-24 15:36:19 +0000 |
| commit | 16ebc9831f156a03bd5ecd21e9365c09bfc43554 (patch) | |
| tree | a1044cb460a377157d111de6f9a7b297c6b338c9 /src/mainboard/siemens/mc_apl1 | |
| parent | 9116eb660eac5fe906f8968704f3daa739c1a8e9 (diff) | |
| download | coreboot-16ebc9831f156a03bd5ecd21e9365c09bfc43554.tar.xz | |
siemens/mc_apl1: Select DDR50 mode for eMMC
To increase the lifetime of the circuit, it is necessary to reduce the
eMMC speed to DDR50 mode.
Change-Id: I40658b44a99e6600ed00950a1a177961f0055e7a
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/28283
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src/mainboard/siemens/mc_apl1')
| -rw-r--r-- | src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb index a273a5983f..f3e8a77143 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb @@ -43,6 +43,9 @@ chip soc/intel/apollolake # [6:0] steps of delay for HS200, each 125ps. register "emmc_rx_cmd_data_cntl2" = "0x10008" + # 0:HS400(Default), 1:HS200, 2:DDR50 + register "emmc_host_max_speed" = "2" + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | |