diff options
| author | Mario Scheithauer <mario.scheithauer@siemens.com> | 2018-11-08 13:49:24 +0100 |
|---|---|---|
| committer | Werner Zeh <werner.zeh@siemens.com> | 2018-11-12 07:26:13 +0000 |
| commit | 4946804f0b6536df3e7a46654c0dbbc3172b1de8 (patch) | |
| tree | 291330d78456374b1799d9e4713a413469aee2a3 /src/mainboard/siemens/mc_apl1 | |
| parent | 04ea73ee78bceb680a2565777c4c7774c2ad1a8e (diff) | |
| download | coreboot-4946804f0b6536df3e7a46654c0dbbc3172b1de8.tar.xz | |
siemens/mc_apl3: Disable PCI clock outputs on XIO bridges
On this mainboard there are legacy PCI device, which are connected to
different PCIe root ports via PCIe-2-PCI bridges. This patch disables
the unused PCI clock outputs on the XIO2001 PCI Express to PCI Bridges.
Change-Id: I2212c1080b72a656b5c8e68b040108a7adbec608
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/29549
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src/mainboard/siemens/mc_apl1')
| -rw-r--r-- | src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c | 22 |
1 files changed, 17 insertions, 5 deletions
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c index 3a87a4f5c5..c436b02d86 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c @@ -40,11 +40,6 @@ void variant_mainboard_final(void) */ pcr_write16(PID_ITSS, 0x314c, 0x2103); - /* Disable clock outputs 1-5 (CLKOUT) for XIO2001 PCIe to PCI Bridge. */ - dev = dev_find_device(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2001, 0); - if (dev) - pci_write_config8(dev, 0xd8, 0x3e); - /* Enable CLKRUN_EN for power gating LPC */ lpc_enable_pci_clk_cntl(); @@ -62,6 +57,23 @@ void variant_mainboard_final(void) cmd = pci_read_config16(dev, PCI_COMMAND); cmd |= PCI_COMMAND_MASTER; pci_write_config16(dev, PCI_COMMAND, cmd); + + /* Disable clock outputs 0 and 2-4 (CLKOUT) for upstream + * XIO2001 PCIe to PCI Bridge. + */ + struct device *parent = dev->bus->dev; + if (parent && parent->device == PCI_DEVICE_ID_TI_XIO2001) + pci_write_config8(parent, 0xd8, 0x1d); + } + + /* Disable clock outputs 2-5 (CLKOUT) for another XIO2001 PCIe to PCI + * Bridge on this mainboard. + */ + dev = dev_find_device(PCI_VENDOR_ID_SIEMENS, 0x403f, 0); + if (dev) { + struct device *parent = dev->bus->dev; + if (parent && parent->device == PCI_DEVICE_ID_TI_XIO2001) + pci_write_config8(parent, 0xd8, 0x3c); } /* Set Full Reset Bit in Reset Control Register (I/O port CF9h). |