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| author | Mario Scheithauer <mario.scheithauer@siemens.com> | 2018-11-23 11:02:17 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-11-27 08:46:46 +0000 |
| commit | 6c3912f0bfe659302df084f9eea0e1feb0b3e3b9 (patch) | |
| tree | c770d7b0458f01eef81924d18f7cee3b4331bdd7 /src/mainboard/siemens/mc_apl1 | |
| parent | 015b3dc124a448e20ea3b3f98decfae5dac26827 (diff) | |
| download | coreboot-6c3912f0bfe659302df084f9eea0e1feb0b3e3b9.tar.xz | |
siemens/mc_apl5: Adjust the settings for the PCIe root ports
This mainboard has four connected PCIe devices. The required root ports
are switched on and configured.
Change-Id: I82b13e1d245a172762ebd689ae136a762027033f
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/29810
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/siemens/mc_apl1')
| -rw-r--r-- | src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb index f3e8a77143..7dbeea15f1 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb @@ -7,12 +7,12 @@ chip soc/intel/apollolake register "sci_irq" = "SCIS_IRQ10" # Disable unused clkreq of PCIe root ports - register "pcie_rp_clkreq_pin[0]" = "3" # PCIe-PCI-Bridge - register "pcie_rp_clkreq_pin[1]" = "2" # FPGA - register "pcie_rp_clkreq_pin[2]" = "0" # MACPHY - register "pcie_rp_clkreq_pin[3]" = "1" # MACPHY - register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED" - register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[0]" = "1" # 14.0 + register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED" # 14.1 + register "pcie_rp_clkreq_pin[2]" = "0" # 13.0 + register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED" # 13.1 + register "pcie_rp_clkreq_pin[4]" = "2" # 13.2 + register "pcie_rp_clkreq_pin[5]" = "3" # 13.3 # EMMC TX DATA Delay 1 # Refer to EDS-Vol2-22.3. @@ -71,12 +71,12 @@ chip soc/intel/apollolake device pci 0e.0 off end # - Audio device pci 11.0 on end # - ISH device pci 12.0 on end # - SATA - device pci 13.0 on end # - RP 2 - PCIe A 0 - MACPHY - device pci 13.1 on end # - RP 3 - PCIe A 1 - MACPHY - device pci 13.2 off end # - RP 4 - PCIe-A 2 - device pci 13.3 off end # - RP 5 - PCIe-A 3 - device pci 14.0 on end # - RP 0 - PCIe-B 0 - PCIe-PCI-Bridge - device pci 14.1 on end # - RP 1 - PCIe-B 1 - FPGA + device pci 13.0 on end # - RP 2 - PCIe A 0 + device pci 13.1 off end # - RP 3 - PCIe A 1 + device pci 13.2 on end # - RP 4 - PCIe-A 2 + device pci 13.3 on end # - RP 5 - PCIe-A 3 + device pci 14.0 on end # - RP 0 - PCIe-B 0 + device pci 14.1 off end # - RP 1 - PCIe-B 1 device pci 15.0 on end # - XHCI device pci 15.1 off end # - XDCI device pci 16.0 on # - I2C 0 |