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| author | Mario Scheithauer <mario.scheithauer@siemens.com> | 2018-11-06 14:59:11 +0100 |
|---|---|---|
| committer | Werner Zeh <werner.zeh@siemens.com> | 2018-11-12 07:25:07 +0000 |
| commit | 98689df18f7431c69cc0b53a53d083ab3cef28ce (patch) | |
| tree | b37c74629ea8a1de98b56d4f224e57423e8e4650 /src/mainboard/siemens/mc_apl1 | |
| parent | cd40ddfad8c0a9f8dc5bf374b44729b9f6a91854 (diff) | |
| download | coreboot-98689df18f7431c69cc0b53a53d083ab3cef28ce.tar.xz | |
siemens/mc_apl3: Adjust Legacy IRQ routing for PCI devices
On this mainboard there is a legacy PCI device, which is connected to
the PCIe root port via a PCIe-2-PCI bridge. This device only supports
legacy interrupt routing. For this reason we have to adjust the PIR6
register (0x314c) which is responsible for PCIe device 13h and 14h. This
means that the interrupt routing will also be the same for both PCIe
devices. The bridge is connected to PCIe root port 2 and 3 over two
lanes (Device 13.0 and 13.1).
The following routing is required:
INTA#->PIRQD#, INTB#->PIRQA#, INTC#->PIRQB#, INTD#->PIRQC#
Change-Id: I5028c26769a2122b1c609ad7789c9949e3cb7a87
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/29513
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/siemens/mc_apl1')
| -rw-r--r-- | src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c index ccf3ab8ec1..ade923a65e 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c @@ -32,11 +32,10 @@ void variant_mainboard_final(void) { struct device *dev = NULL; - /* - * PIR6 register mapping for PCIe root ports - * INTA#->PIRQB#, INTB#->PIRQC#, INTC#->PIRQD#, INTD#-> PIRQA# + /* PIR6 register mapping for PCIe root ports + * INTA#->PIRQD#, INTB#->PIRQA#, INTC#->PIRQB#, INTD#-> PIRQC# */ - pcr_write16(PID_ITSS, 0x314c, 0x0321); + pcr_write16(PID_ITSS, 0x314c, 0x2103); /* Disable clock outputs 1-5 (CLKOUT) for XIO2001 PCIe to PCI Bridge. */ dev = dev_find_device(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2001, 0); |