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author | Elyes HAOUAS <ehaouas@noos.fr> | 2016-09-19 09:47:16 -0600 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2016-09-20 21:55:12 +0200 |
commit | a5aad2ed68690d748c650f69a2e39f91a7b02608 (patch) | |
tree | 7ad419bc13bcf13e546481558aa1a4c923821c07 /src/mainboard/siemens/sitemp_g1p1/romstage.c | |
parent | 531b87ac4e8038aedf9c44c29fe2c1fc31adb346 (diff) | |
download | coreboot-a5aad2ed68690d748c650f69a2e39f91a7b02608.tar.xz |
src/mainboard/lenovo-winent: Add space around operators
Change-Id: Iab2a879ebdea9d93ef5eb7e3abf875036c1e1cb4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16641
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard/siemens/sitemp_g1p1/romstage.c')
-rw-r--r-- | src/mainboard/siemens/sitemp_g1p1/romstage.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/siemens/sitemp_g1p1/romstage.c b/src/mainboard/siemens/sitemp_g1p1/romstage.c index 634f974e48..a7f2c965d4 100644 --- a/src/mainboard/siemens/sitemp_g1p1/romstage.c +++ b/src/mainboard/siemens/sitemp_g1p1/romstage.c @@ -141,7 +141,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if( (cpuid1.edx & 0x6) == 0x6 ) { /* Read FIDVID_STATUS */ - msr=rdmsr(0xc0010042); + msr = rdmsr(0xc0010042); __DEBUG__("begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); enable_fid_change(); @@ -149,7 +149,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) init_fidvid_bsp(bsp_apicid); /* show final fid and vid */ - msr=rdmsr(0xc0010042); + msr = rdmsr(0xc0010042); __DEBUG__("end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); } else { |