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authorAndrey Petrov <andrey.petrov@intel.com>2017-06-05 18:24:50 -0700
committerAaron Durbin <adurbin@chromium.org>2017-07-13 19:28:53 +0000
commit9f244a5494192707bfbb72e60f17411e9a35434a (patch)
treeb50c1796879e4531c124c22837751e5af49dd632 /src/mainboard/siemens/sitemp_g1p1
parentf35804ba6f14d748568119206bdfe26046c9606b (diff)
downloadcoreboot-9f244a5494192707bfbb72e60f17411e9a35434a.tar.xz
soc/intel/cannonlake: Add Makefile
This enables building working bootblock and non-functional romstage and ramstage. Change-Id: I580cd2c3279d742f202b2adfbe55c814cfb48f99 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/20073 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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