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| author | peichao.wang <peichao.wang@bitland.corp-partner.google.com> | 2018-09-12 13:55:46 +0800 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2018-09-14 08:26:04 +0000 |
| commit | 211ceb5976e06cd85ca1f65d7dea116a7d92d451 (patch) | |
| tree | 98d9acd7222cef0de64ab52e2165cba46fde5187 /src/mainboard/siemens | |
| parent | 75a62e76486f63f6dadb5492c205570ace81e9d5 (diff) | |
| download | coreboot-211ceb5976e06cd85ca1f65d7dea116a7d92d451.tar.xz | |
mb/google/octopus: fetch DRAM part number from CBI for phaser after DVT phase
This modification for DVT build and use CBI method
enable all memory particles.
BUG=b:112870780
TEST=verify it under the EVT unit and pre-test EVT
unit(rework RAM ID follow the proposal) respectively.
Change-Id: I488a0652ba348eff9a6d8591b0cfa6ed4fe808aa
Signed-off-by: peichao.wang <peichao.wang@bitland.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/28579
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/siemens')
0 files changed, 0 insertions, 0 deletions