diff options
| author | Furquan Shaikh <furquan@google.com> | 2018-03-14 19:57:16 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2018-03-16 04:43:01 +0000 |
| commit | 6d5e10c05d99c475e63bbe95012066f9c585cfb3 (patch) | |
| tree | 8cecb6956bed707c4a8900ab79c491ad87982698 /src/mainboard/siemens | |
| parent | 211bb97c67ce704fb40abb6dd9971790652237e3 (diff) | |
| download | coreboot-6d5e10c05d99c475e63bbe95012066f9c585cfb3.tar.xz | |
soc/intel/apollolake and mainboards: Use pcie_rp_clkreq_pin array
This change uses an array pcie_rp_clkreq_pin for accepting CLKREQ#
from mainboards instead of defining a separate property for each root
port. This allows us to use memcpy to copy the entire array into FSP
params as well as new properties for PCIe root ports can be added as
arrays in future CLs.
BUG=b:74633273
BRANCH=reef,coral
Change-Id: Ifa05f1e38fcfd95063ec327712e472cdbd12dbb7
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/25186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/siemens')
| -rw-r--r-- | src/mainboard/siemens/mc_apl1/devicetree.cb | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/mainboard/siemens/mc_apl1/devicetree.cb b/src/mainboard/siemens/mc_apl1/devicetree.cb index e2b6ceec7f..c1ef76b649 100644 --- a/src/mainboard/siemens/mc_apl1/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/devicetree.cb @@ -7,12 +7,12 @@ chip soc/intel/apollolake register "sci_irq" = "SCIS_IRQ10" # Disable unused clkreq of PCIe root ports - register "pcie_rp0_clkreq_pin" = "3" # PCIe-PCI-Bridge - register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED" - register "pcie_rp2_clkreq_pin" = "0" # MACPHY - register "pcie_rp3_clkreq_pin" = "1" # MACPHY - register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED" - register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[0]" = "3" # PCIe-PCI-Bridge + register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[2]" = "0" # MACPHY + register "pcie_rp_clkreq_pin[3]" = "1" # MACPHY + register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED" # EMMC TX DATA Delay 1 # Refer to EDS-Vol2-22.3. |