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| author | Angel Pons <th3fanbus@gmail.com> | 2020-11-02 22:49:51 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-04-21 09:06:30 +0000 |
| commit | f8a5eb2e4afc190214ba5f1766998a1812f69a40 (patch) | |
| tree | aa8b375900a20bd721ceb113fe335110e47684de /src/mainboard/siemens | |
| parent | 0b7813fe97121eb7cb9c0b8ac59e604e9f613679 (diff) | |
| download | coreboot-f8a5eb2e4afc190214ba5f1766998a1812f69a40.tar.xz | |
mainboard: Use read_int_option()
Change-Id: I9273b90b6a21b8f52fa42d9ff03a9b56eec9fcbf
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47137
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard/siemens')
| -rw-r--r-- | src/mainboard/siemens/chili/romstage.c | 6 | ||||
| -rw-r--r-- | src/mainboard/siemens/chili/variants/chili/romstage.c | 3 |
2 files changed, 4 insertions, 5 deletions
diff --git a/src/mainboard/siemens/chili/romstage.c b/src/mainboard/siemens/chili/romstage.c index 06927b0eff..330d8afdc2 100644 --- a/src/mainboard/siemens/chili/romstage.c +++ b/src/mainboard/siemens/chili/romstage.c @@ -9,7 +9,6 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) { - uint8_t vtd = 1; const struct cnl_mb_cfg cfg = { .spd = { [0] = { READ_SMBUS, { 0x50 << 1 } }, @@ -25,9 +24,10 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) memupd->FspmConfig.EccSupport = 1; memupd->FspmConfig.UserBd = BOARD_TYPE_MOBILE; - get_option(&vtd, "vtd"); + const uint8_t vtd = get_int_option("vtd", 1); memupd->FspmTestConfig.VtdDisable = !vtd; - get_option(&memupd->FspmConfig.HyperThreading, "hyper_threading"); + const uint8_t ht = get_int_option("hyper_threading", memupd->FspmConfig.HyperThreading); + memupd->FspmConfig.HyperThreading = ht; variant_romstage_params(memupd); diff --git a/src/mainboard/siemens/chili/variants/chili/romstage.c b/src/mainboard/siemens/chili/variants/chili/romstage.c index 3a838240ef..fadd2b77b5 100644 --- a/src/mainboard/siemens/chili/variants/chili/romstage.c +++ b/src/mainboard/siemens/chili/variants/chili/romstage.c @@ -7,9 +7,8 @@ void variant_romstage_params(FSPM_UPD *const mupd) { - uint8_t eth_enable = 1; + const uint8_t eth_enable = get_int_option("ethernet1", 1); - get_option(ð_enable, "ethernet1"); if (!eth_enable) { printk(BIOS_DEBUG, "Disabling ethernet1.\n"); mupd->FspmConfig.PcieRpEnableMask &= ~(1 << 5); |