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authorMarshall Dawson <marshalldawson3rd@gmail.com>2018-04-09 22:15:06 -0600
committerMartin Roth <martinroth@google.com>2018-04-11 14:13:56 +0000
commit8f031d8234212266a6a18747415550ae5b89c776 (patch)
tree3d26310924fa9ee472e5fb9a7fd1adfbe29fb4fa /src/mainboard/siemens
parentfbc66b9dc035bcd287d434363ce984c41118bf95 (diff)
downloadcoreboot-8f031d8234212266a6a18747415550ae5b89c776.tar.xz
amd/stoneyridge: Reorder temp mtrr for flash
Relocate setting the temp range MTRR, for the SPI flash device, to after completion of mp_init. The mp_init functionality mirrors the BSP's exact MTRR settings into the AP cores. The ranges need to be the correct calculated values and not some temporary setting. This solves an MTRR sync issue on APUs with more than two cores, i.e. more than a single compute-unit. MTRRs within a CU are shared so the AP always stays in sync. BUG=b:77457944 TEST=run on Kahlee Change-Id: Idc4cccdf721e252bc87d6cba62a3406a9f19b940 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/25575 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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