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authorWerner Zeh <werner.zeh@siemens.com>2019-02-01 12:39:40 +0100
committerWerner Zeh <werner.zeh@siemens.com>2019-02-05 06:34:53 +0000
commitd7e5f4b7c50eacf033154e2514a6bef3db80d4b5 (patch)
tree04079ece4b71f492395d606c35e2a018574eed0f /src/mainboard/siemens
parent279afdc24b3c65275cad222be53b908bb0f752ef (diff)
downloadcoreboot-d7e5f4b7c50eacf033154e2514a6bef3db80d4b5.tar.xz
mb/siemens/mc_apl1: Enable VTD for mc_apl2 and mc_apl5
These boards need a working VTD therefore enable this feature. Change-Id: I74c64bf1bd66188c4c32b85c66683dafd0e1fd38 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/31195 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Diffstat (limited to 'src/mainboard/siemens')
-rw-r--r--src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb3
-rw-r--r--src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb3
2 files changed, 6 insertions, 0 deletions
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb
index c362e6c0a9..7a0b8863d7 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb
@@ -47,6 +47,9 @@ chip soc/intel/apollolake
# 0:HS400(Default), 1:HS200, 2:DDR50
register "emmc_host_max_speed" = "2"
+ # Enable Vtd feature
+ register "enable_vtd" = "1"
+
device domain 0 on
device pci 00.0 on end # - Host Bridge
device pci 00.1 off end # - DPTF
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb
index dfdfd551b4..989ab45699 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb
@@ -46,6 +46,9 @@ chip soc/intel/apollolake
# 0:HS400(Default), 1:HS200, 2:DDR50
register "emmc_host_max_speed" = "2"
+ # Enable Vtd feature
+ register "enable_vtd" = "1"
+
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |