siemens/mc_apl4: Clean up ramstage

Currently, there is nothing for this mainboard to do in ramstage.

Change-Id: Id74a5f3f0a0583dc6bc81044913b8bb83d3b0b93
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/29632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>

3 files changed, 0 insertions, 104 deletions

diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig
index 3cf7406020..ea81c6ce13 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig
@@ -4,10 +4,6 @@ if BOARD_SIEMENS_MC_APL4
 config BOARD_SIEMENS_MC_APL4_VAR
 	def_bool y
 	select DRIVER_INTEL_I210
-	select DRIVERS_I2C_RX6110SA
-	select DRIVER_SIEMENS_NC_FPGA
-	select NC_FPGA_NOTIFY_CB_READY
-	select APL_SKIP_SET_POWER_LIMITS
 
 config DEVICETREE
 	string
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Makefile.inc b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Makefile.inc
index caf542fcd2..fd45b948ff 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Makefile.inc
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Makefile.inc
@@ -1,3 +1 @@
 romstage-y += memory.c
-
-ramstage-y += mainboard.c
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/mainboard.c
deleted file mode 100644
index ccf3ab8ec1..0000000000
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/mainboard.c
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2018 Siemens AG
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <bootstate.h>
-#include <console/console.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include <gpio.h>
-#include <hwilib.h>
-#include <intelblocks/lpc_lib.h>
-#include <intelblocks/pcr.h>
-#include <soc/pcr_ids.h>
-#include <timer.h>
-#include <timestamp.h>
-#include <baseboard/variants.h>
-
-#define TX_DWORD3	0xa8c
-
-void variant_mainboard_final(void)
-{
-	struct device *dev = NULL;
-
-	/*
-	 * PIR6 register mapping for PCIe root ports
-	 * INTA#->PIRQB#, INTB#->PIRQC#, INTC#->PIRQD#, INTD#-> PIRQA#
-	 */
-	pcr_write16(PID_ITSS, 0x314c, 0x0321);
-
-	/* Disable clock outputs 1-5 (CLKOUT) for XIO2001 PCIe to PCI Bridge. */
-	dev = dev_find_device(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2001, 0);
-	if (dev)
-		pci_write_config8(dev, 0xd8, 0x3e);
-
-	/* Enable CLKRUN_EN for power gating LPC */
-	lpc_enable_pci_clk_cntl();
-
-	/*
-	 * Enable LPC PCE (Power Control Enable) by setting IOSF-SB port 0xD2
-	 * offset 0x341D bit3 and bit0.
-	 * Enable LPC CCE (Clock Control Enable) by setting IOSF-SB port 0xD2
-	 * offset 0x341C bit [3:0].
-	 */
-	pcr_or32(PID_LPC, PCR_LPC_PRC, (PCR_LPC_CCE_EN | PCR_LPC_PCE_EN));
-
-	/*
-	 * Correct the SATA transmit signal via the High Speed I/O Transmit
-	 * Control Register 3.
-	 * Bit [23:16] set the output voltage swing for TX line.
-	 * The value 0x4a sets the swing level to 0.58 V.
-	 */
-	pcr_rmw32(PID_MODPHY, TX_DWORD3, (0x00 << 16), (0x4a << 16));
-}
-
-static void wait_for_legacy_dev(void *unused)
-{
-	uint32_t legacy_delay, us_since_boot;
-	struct stopwatch sw;
-
-	/* Open main hwinfo block. */
-	if (hwilib_find_blocks("hwinfo.hex") != CB_SUCCESS)
-		return;
-
-	/* Get legacy delay parameter from hwinfo. */
-	if (hwilib_get_field(LegacyDelay, (uint8_t *) &legacy_delay,
-			      sizeof(legacy_delay)) != sizeof(legacy_delay))
-		return;
-
-	us_since_boot = get_us_since_boot();
-	/* No need to wait if the time since boot is already long enough.*/
-	if (us_since_boot > legacy_delay)
-		return;
-	stopwatch_init_msecs_expire(&sw, (legacy_delay - us_since_boot) / 1000);
-	printk(BIOS_NOTICE, "Wait remaining %d of %d us for legacy devices...",
-			legacy_delay - us_since_boot, legacy_delay);
-	stopwatch_wait_until_expired(&sw);
-	printk(BIOS_NOTICE, "done!\n");
-}
-
-static void finalize_boot(void *unused)
-{
-	/* Set coreboot ready LED. */
-	gpio_output(CNV_RGI_DT, 1);
-}
-
-BOOT_STATE_INIT_ENTRY(BS_DEV_ENUMERATE, BS_ON_ENTRY, wait_for_legacy_dev, NULL);
-BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, finalize_boot, NULL);