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| author | Mario Scheithauer <mario.scheithauer@siemens.com> | 2018-11-28 09:21:58 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-11-29 12:17:32 +0000 |
| commit | 1a5ce95815210032783d01e830390ee5b6a54dc5 (patch) | |
| tree | 2355cc04a346d505bda93f8fa316e79cde858e38 /src/mainboard/siemens | |
| parent | a94a153477584ba2d168021f23fa571f048e6767 (diff) | |
| download | coreboot-1a5ce95815210032783d01e830390ee5b6a54dc5.tar.xz | |
siemens/mc_apl5: Disable PCI clock outputs on XIO bridges
On this mainboard there are legacy PCI device, which are connected to
different PCIe root ports via PCIe-2-PCI bridges. This patch disables
the unused PCI clock outputs on the XIO2001 PCI Express to PCI Bridges.
Change-Id: Id36e39c4568f5dd241cd864d2e75365abd0f2a91
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/29882
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/siemens')
| -rw-r--r-- | src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c | 21 |
1 files changed, 16 insertions, 5 deletions
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c index 06b2a2fc92..9462497aa6 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c @@ -52,11 +52,6 @@ void variant_mainboard_final(void) */ pcr_write16(PID_ITSS, 0x314c, 0x0321); - /* Disable clock outputs 1-5 (CLKOUT) for XIO2001 PCIe to PCI Bridge. */ - dev = dev_find_device(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2001, 0); - if (dev) - pci_write_config8(dev, 0xd8, 0x3e); - /* Enable CLKRUN_EN for power gating LPC */ lpc_enable_pci_clk_cntl(); @@ -82,6 +77,22 @@ void variant_mainboard_final(void) cmd = pci_read_config16(dev, PCI_COMMAND); cmd |= PCI_COMMAND_MASTER; pci_write_config16(dev, PCI_COMMAND, cmd); + + /* Disable clock outputs 0-3 (CLKOUT) for upstream XIO2001 PCIe + * to PCI Bridge. */ + struct device *parent = dev->bus->dev; + if (parent && parent->device == PCI_DEVICE_ID_TI_XIO2001) + pci_write_config8(parent, 0xd8, 0x0f); + } + + /* Disable clock outputs 1-5 (CLKOUT) for another XIO2001 PCIe to PCI + * Bridge on this mainboard. + */ + dev = dev_find_device(PCI_VENDOR_ID_SIEMENS, 0x403f, 0); + if (dev) { + struct device *parent = dev->bus->dev; + if (parent && parent->device == PCI_DEVICE_ID_TI_XIO2001) + pci_write_config8(parent, 0xd8, 0x3e); } } |