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| author | Tim Chen <Tim-Chen@quantatw.com> | 2017-03-07 14:45:15 +0800 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-03-10 19:48:08 +0100 |
| commit | 327c5c60ddc14e5f466c7a2f9ac6dcfb4d9f4941 (patch) | |
| tree | 10029f44f9ebbd5fa314015ab685a0525a60c6a4 /src/mainboard/siemens | |
| parent | e392f414cd27edba78f02a5e9274126aa0a80f89 (diff) | |
| download | coreboot-327c5c60ddc14e5f466c7a2f9ac6dcfb4d9f4941.tar.xz | |
mainboard/google/reef: Modify TCPU, TSR2 and TRT table
Update the DPTF parameters based on thermal test result.
(ZHT_DPTF_EVT2_v0.5_20170306.xlsx)
1. Update DPTF TCPU critical trigger point.
TCPU critical point: 105
2. Update DPTF TSR2 passive trigger point.
TSR2 passive point: 58
3. Change thermal relationship table (TRT) setting.
Change CPU Throttle Effect on CPU sample rate to 10secs.
Change Charger Effect on Temp Sensor 2 sample rate to 30secs.
Change CPU Effect on Temp Sensor 2 sample rate to 60secs.
BUG=b:35583586
BRANCH=master
TEST=build and boot on electro dut
Change-Id: I85564ccdaf327eeaa13bf1f31d9a933609a21582
Signed-off-by: Tim Chen <Tim-Chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/18610
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/mainboard/siemens')
0 files changed, 0 insertions, 0 deletions