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| author | Mario Scheithauer <mario.scheithauer@siemens.com> | 2018-11-07 08:36:14 +0100 |
|---|---|---|
| committer | Werner Zeh <werner.zeh@siemens.com> | 2018-11-12 07:25:21 +0000 |
| commit | bcbcecd38ff6273bb9e8bf45da8e5f1578a72728 (patch) | |
| tree | 3ecf26fdff521c655613095763c14efc9aef1aeb /src/mainboard/siemens | |
| parent | 98689df18f7431c69cc0b53a53d083ab3cef28ce (diff) | |
| download | coreboot-bcbcecd38ff6273bb9e8bf45da8e5f1578a72728.tar.xz | |
siemens/mc_apl3: Remove the correction of the Tx signal for SATA
For this mainboard the correction of transmit voltage swing from SATA
interface is not necessary.
Change-Id: I900d0d44b88585c223182d85c78cf3ff1e3e9159
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/29527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src/mainboard/siemens')
| -rw-r--r-- | src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c | 8 |
1 files changed, 0 insertions, 8 deletions
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c index ade923a65e..bfcf38ef5f 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c @@ -52,14 +52,6 @@ void variant_mainboard_final(void) * offset 0x341C bit [3:0]. */ pcr_or32(PID_LPC, PCR_LPC_PRC, (PCR_LPC_CCE_EN | PCR_LPC_PCE_EN)); - - /* - * Correct the SATA transmit signal via the High Speed I/O Transmit - * Control Register 3. - * Bit [23:16] set the output voltage swing for TX line. - * The value 0x4a sets the swing level to 0.58 V. - */ - pcr_rmw32(PID_MODPHY, TX_DWORD3, (0x00 << 16), (0x4a << 16)); } static void wait_for_legacy_dev(void *unused) |