diff options
author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2019-08-27 15:07:37 +0200 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2019-09-12 13:16:24 +0000 |
commit | d589c8681ebaa9b45168a23c8d3fe522e776b0f4 (patch) | |
tree | f3d48eb7fde0d8749c7da4a44d674b29825935d5 /src/mainboard/sifive/hifive-unleashed/hifive-unleashed-a00.dts | |
parent | c27014b9dfdee65a26c7ea2d6dc6d0da7cfa218e (diff) | |
download | coreboot-d589c8681ebaa9b45168a23c8d3fe522e776b0f4.tar.xz |
mainboard/sifive/hifive-unleashed: Update devicetree
With the current devicetree the kernel doesn't provide any serial
after serial init.
Update the devicetree to resolve this issue.
Tested on HiFive Unleashed.
Change-Id: I4427d34a12902e0eaa2186121a53152b719cadff
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Hug <philipp@hug.cx>
Diffstat (limited to 'src/mainboard/sifive/hifive-unleashed/hifive-unleashed-a00.dts')
-rw-r--r-- | src/mainboard/sifive/hifive-unleashed/hifive-unleashed-a00.dts | 97 |
1 files changed, 97 insertions, 0 deletions
diff --git a/src/mainboard/sifive/hifive-unleashed/hifive-unleashed-a00.dts b/src/mainboard/sifive/hifive-unleashed/hifive-unleashed-a00.dts new file mode 100644 index 0000000000..454c3d807c --- /dev/null +++ b/src/mainboard/sifive/hifive-unleashed/hifive-unleashed-a00.dts @@ -0,0 +1,97 @@ +/* + * This file is part of the Linux kernel. + * + * Copyright (c) 2018-2019 SiFive, Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/include/ "fu540-c000.dtsi" + +/ { + #address-cells = <2>; + #size-cells = <2>; + model = "SiFive HiFive Unleashed A00"; + compatible = "sifive,hifive-unleashed-a00", "sifive,fu540-c000"; + + chosen { + }; + + cpus { + /* Clock frequency (in Hz) of the PCB crystal for rtcclk */ + timebase-frequency = <1000000>; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x2 0x00000000>; + }; + + soc { + }; + + hfclk: hfclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <33333333>; + clock-output-names = "hfclk"; + }; + + rtcclk: rtcclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <1000000>; + clock-output-names = "rtcclk"; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&qspi0 { + status = "okay"; + flash@0 { + compatible = "issi,is25wp256", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + m25p,fast-read; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&qspi2 { + status = "okay"; + mmc@0 { + compatible = "mmc-spi-slot"; + reg = <0>; + spi-max-frequency = <20000000>; + voltage-ranges = <3300 3300>; + disable-wp; + }; +}; + +ð0 { + status = "okay"; + phy-mode = "gmii"; + phy-handle = <&phy0>; + phy0: ethernet-phy@0 { + reg = <0>; + }; +}; |