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authorPhilipp Hug <philipp@hug.cx>2018-09-13 22:18:06 +0200
committerRonald G. Minnich <rminnich@gmail.com>2018-09-14 10:32:20 +0000
commit91595724e7f302e0a876f0507e307f37f5871a7d (patch)
tree47ce93e077716930744d92be13307e5b721c7715 /src/mainboard/sifive
parent95c331b94b1d04ea34b480c83613c2141a02697e (diff)
downloadcoreboot-91595724e7f302e0a876f0507e307f37f5871a7d.tar.xz
soc/sifive/fu540: Initialize SDRAM
Based on SiFive bootloader code Change-Id: I71043ce9e458e25e64da28d53cd36b02d2e22acc Signed-off-by: Philipp Hug <philipp@hug.cx> Reviewed-on: https://review.coreboot.org/28604 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/sifive')
-rw-r--r--src/mainboard/sifive/hifive-unleashed/romstage.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/sifive/hifive-unleashed/romstage.c b/src/mainboard/sifive/hifive-unleashed/romstage.c
index 9729f86f4a..df4cf894b2 100644
--- a/src/mainboard/sifive/hifive-unleashed/romstage.c
+++ b/src/mainboard/sifive/hifive-unleashed/romstage.c
@@ -40,5 +40,7 @@ void main(void)
uart_init(CONFIG_UART_FOR_CONSOLE);
#endif
+ sdram_init();
+
run_ramstage();
}