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| author | Karthikeyan Ramasubramanian <kramasub@chromium.org> | 2018-12-26 21:51:06 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-01-24 13:54:40 +0000 |
| commit | 0b5d2e0f0bd9358c9405965eea10db8eebf49d5a (patch) | |
| tree | fa6b9e83d36a2461afd9ce6e1e0eddcddd9f37d2 /src/mainboard/sifive | |
| parent | ab0a77453c86fe01ef142fcf1df5e1c11a16daf2 (diff) | |
| download | coreboot-0b5d2e0f0bd9358c9405965eea10db8eebf49d5a.tar.xz | |
soc/intel/common/gpio_defs: Enable configuring GPIO_DW2 pad register
Currently all the helpers support configuring GPIO_DW0/1 registers. In
some architectures there is an additional configuration GPIO_DW2 register
that can be used to configure debounce duration etc. Add a helper macro
to enable configuring GPIO_DW2 pad register.
BRANCH=octopus
BUG=b:117953118
TEST=Ensure that the system boots to ChromeOS. Ensure that the current
configuration is not disturbed by turning on the GPIO_DEBUG option and
verifying the debug output before and after the change.
Change-Id: I3e5d259d007fdc83940a43cc4cd4a2b8a547d334
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@chromium.org>
Reviewed-on: https://review.coreboot.org/c/30449
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/sifive')
0 files changed, 0 insertions, 0 deletions