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| author | Stefan Reinauer <stepan@coresystems.de> | 2010-03-31 14:34:40 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2010-03-31 14:34:40 +0000 |
| commit | 5a1f5970857a5ad1fda0cf9d5945192408bf537b (patch) | |
| tree | b81a16a564c29788dcb6c306ea27855703d230de /src/mainboard/soyo/sy-6ba-plus-iii | |
| parent | b8ac05d187c6cc4e777c96d39e075c5d97d93ffc (diff) | |
| download | coreboot-5a1f5970857a5ad1fda0cf9d5945192408bf537b.tar.xz | |
This patch drops arch/i386/lib/console.c and arch/i386/lib/console_print.c and
makes include/console/console.h and console/console.c usable both in
__PRE_RAM__ and coreboot_ram stages.
While debugging this, I removed an indirection from the e7520 ram init code
(same as we did on a couple of other chipsets, removes some register pressure
from romcc)
Also, drop remainders of CONFIG_USE_INIT (except the one odd piece of dead code
in cache_as_ram.inc)
Then some ap_romstage.c fixes, at least the nvidia/l1_2pvv compiled for me with
CONFIG_AP_CODE_IN_CAR set in Kconfig which it did not before.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5341 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/soyo/sy-6ba-plus-iii')
| -rw-r--r-- | src/mainboard/soyo/sy-6ba-plus-iii/romstage.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c b/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c index cbf4bd3ea0..1636c42f86 100644 --- a/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c +++ b/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c @@ -26,7 +26,7 @@ #include <arch/hlt.h> #include <stdlib.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" |