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| author | Keith Hui <buurin@gmail.com> | 2017-08-10 20:49:05 -0400 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2017-08-15 21:00:36 +0000 |
| commit | 95f296e47cefe5da950c59b3f4234fffc5fc8a2f (patch) | |
| tree | 9eaae26c19d25c937a4d8ae8096fd5dbe840c283 /src/mainboard/soyo | |
| parent | 0fda9f54c774b73efbd89ae20ed10136fa55dc96 (diff) | |
| download | coreboot-95f296e47cefe5da950c59b3f4234fffc5fc8a2f.tar.xz | |
440BX boards: Use combined RAM init routine
Change all 440BX boards to use the combined RAM init routine added in
commit 078e3240 (northbridge/intel/i440bx: Merge RAM init routines) [1].
[1] https://review.coreboot.org/20676
Change-Id: I699db882189f99018d4a6fdcb00f9438b2a7a1bc
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/20868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/mainboard/soyo')
| -rw-r--r-- | src/mainboard/soyo/sy-6ba-plus-iii/romstage.c | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c b/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c index be79c7503b..0bb1ab2552 100644 --- a/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c +++ b/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c @@ -38,8 +38,5 @@ void mainboard_romstage_entry(unsigned long bist) report_bist_failure(bist); enable_smbus(); - dump_spd_registers(); - sdram_set_registers(); - sdram_set_spd_registers(); - sdram_enable(); + sdram_initialize(); } |