summaryrefslogtreecommitdiff
path: root/src/mainboard/soyo
diff options
context:
space:
mode:
authorStefan Reinauer <reinauer@chromium.org>2013-02-12 14:17:15 -0800
committerRonald G. Minnich <rminnich@gmail.com>2013-02-14 02:00:10 +0100
commit4aff4458f58398f54c248604694c7005294c1747 (patch)
treeeb3d9259255abc486a4d6d9eb53199b4d408053e /src/mainboard/soyo
parentdc8259ce1d2e866f3133da49c1d6f4773f5698c1 (diff)
downloadcoreboot-4aff4458f58398f54c248604694c7005294c1747.tar.xz
sconfig: rename pci_domain -> domain
The name pci_domain was a bit misleading, since the construct is only PCI specific in a particular (northbridge/cpu) implementation, but not by concept. As implementations and hardware change, be more generic about our naming. This will allow us to support non-PCI systems without adding new keywords. Change-Id: Ide885a1d5e15d37560c79b936a39252150560e85 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2376 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/mainboard/soyo')
-rw-r--r--src/mainboard/soyo/sy-6ba-plus-iii/devicetree.cb2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/soyo/sy-6ba-plus-iii/devicetree.cb b/src/mainboard/soyo/sy-6ba-plus-iii/devicetree.cb
index 03451e2421..c39a2ce554 100644
--- a/src/mainboard/soyo/sy-6ba-plus-iii/devicetree.cb
+++ b/src/mainboard/soyo/sy-6ba-plus-iii/devicetree.cb
@@ -24,7 +24,7 @@ chip northbridge/intel/i440bx # Northbridge
device lapic 0 on end # APIC
end
end
- device pci_domain 0 on # PCI domain
+ device domain 0 on # PCI domain
device pci 0.0 on end # Host bridge
device pci 1.0 on end # PCI/AGP bridge
chip southbridge/intel/i82371eb # Southbridge