summaryrefslogtreecommitdiff
path: root/src/mainboard/soyo
diff options
context:
space:
mode:
authorUwe Hermann <uwe@hermann-uwe.de>2010-10-06 19:32:39 +0000
committerUwe Hermann <uwe@hermann-uwe.de>2010-10-06 19:32:39 +0000
commit6f2d20ec490a276a087acad0b3866c0f3ee844c4 (patch)
tree8b96891ff7986129f1cee5c556719fd1edc1aa73 /src/mainboard/soyo
parent5225520172a1d1e5c19a93c9178ecd7b72a13248 (diff)
downloadcoreboot-6f2d20ec490a276a087acad0b3866c0f3ee844c4.tar.xz
Convert all Intel 440BX boards to Cache-as-RAM (CAR).
- Add "select CACHE_AS_RAM" in src/cpu/intel/slot_1/Kconfig. - Add the following in src/cpu/intel/slot_1/Makefile.inc: cpu_incs += $(src)/cpu/intel/car/cache_as_ram.inc - Remove "select ROMCC" from all 440BX board Kconfig files. - Drop all early_mtrr_init() calls, that's done by CAR code now. Various small fixes were needed to make it build: - Drop do_smbus_recv_byte(), do_smbus_send_byte(), do_smbus_write_byte(), those were never called anyways. - Remove the "static" from the main() functions in romstage.c files. - Always call dump_spd_registers() from the 440BX debug.c, but use "#if CONFIG_DEBUG_RAM_SETUP" to only have that code if RAM debugging is enabled in menuconfig. - Drop all "lib/ramtest.c" #includes and ram_check() calls (even if commented out) from romstage.c's, as we've done for most other boards. - Add missing #includes or prototypes. Some of the prototypes will be removed later when we get rid of the #include'd .c files. Abuild-tested for all boards, and boot-tested on A-Trend ATC-6220. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5917 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/soyo')
-rw-r--r--src/mainboard/soyo/sy-6ba-plus-iii/Kconfig1
-rw-r--r--src/mainboard/soyo/sy-6ba-plus-iii/romstage.c13
2 files changed, 4 insertions, 10 deletions
diff --git a/src/mainboard/soyo/sy-6ba-plus-iii/Kconfig b/src/mainboard/soyo/sy-6ba-plus-iii/Kconfig
index bff1bdbc12..d873e1fc3c 100644
--- a/src/mainboard/soyo/sy-6ba-plus-iii/Kconfig
+++ b/src/mainboard/soyo/sy-6ba-plus-iii/Kconfig
@@ -25,7 +25,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select NORTHBRIDGE_INTEL_I440BX
select SOUTHBRIDGE_INTEL_I82371EB
select SUPERIO_ITE_IT8671F
- select ROMCC
select HAVE_PIRQ_TABLE
select UDELAY_TSC
select BOARD_ROMSIZE_KB_256
diff --git a/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c b/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c
index cd5289d414..901d271656 100644
--- a/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c
+++ b/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c
@@ -26,16 +26,16 @@
#include <arch/hlt.h>
#include <stdlib.h>
#include <console/console.h>
-#include "lib/ramtest.c"
#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
#include "northbridge/intel/i440bx/raminit.h"
#include "lib/debug.c"
#include "pc80/udelay_io.c"
#include "lib/delay.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
+void it8671f_48mhz_clkin(void);
#include "superio/ite/it8671f/it8671f_early_serial.c"
+#include <lib.h>
#define SERIAL_DEV PNP_DEV(0x370, IT8671F_SP1)
@@ -47,11 +47,8 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
#include "northbridge/intel/i440bx/raminit.c"
#include "northbridge/intel/i440bx/debug.c"
-static void main(unsigned long bist)
+void main(unsigned long bist)
{
- if (bist == 0)
- early_mtrr_init();
-
it8671f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
@@ -61,10 +58,8 @@ static void main(unsigned long bist)
i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
enable_smbus();
- /* dump_spd_registers(); */
+ dump_spd_registers();
sdram_set_registers();
sdram_set_spd_registers();
sdram_enable();
- /* ram_check(0, 640 * 1024); */
}
-