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| author | Uwe Hermann <uwe@hermann-uwe.de> | 2009-10-04 23:50:06 +0000 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2009-10-04 23:50:06 +0000 |
| commit | 90950925c79b4d0b48c3d9dfc1e3de6a67212a97 (patch) | |
| tree | a608e123d6def08edeeaa16075a8fe6fbf2bdeec /src/mainboard/soyo | |
| parent | 24796fd364176ce8bb4f4eb727e0ba2ece188c08 (diff) | |
| download | coreboot-90950925c79b4d0b48c3d9dfc1e3de6a67212a97.tar.xz | |
The new CBFS based build system requires the whole ROM to be accessible
in very early stages, otherwise the boot may hang like this because
the CBFS headers cannot be found/accessed:
Uncompressing coreboot to RAM.
Jumping to image.
Check CBFS header at fffedfe0
magic is ffffffff
ERROR: No valid CBFS header found!
CBFS: Could not find file fallback/coreboot_ram
Jumping to image.
This patch enables full ROM access on all 440BX boards right after the
serial init (and before CBFS headers are parsed).
Build-tested and runtime-tested on ASUS P2B-F.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4721 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/soyo')
| -rw-r--r-- | src/mainboard/soyo/sy-6ba-plus-iii/auto.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/mainboard/soyo/sy-6ba-plus-iii/auto.c b/src/mainboard/soyo/sy-6ba-plus-iii/auto.c index 81241ac553..72c5f58831 100644 --- a/src/mainboard/soyo/sy-6ba-plus-iii/auto.c +++ b/src/mainboard/soyo/sy-6ba-plus-iii/auto.c @@ -30,6 +30,7 @@ #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "lib/ramtest.c" +#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c" @@ -58,6 +59,10 @@ static void main(unsigned long bist) uart_init(); console_init(); report_bist_failure(bist); + + /* Enable access to the full ROM chip, needed very early by CBFS. */ + i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */ + enable_smbus(); /* dump_spd_registers(); */ sdram_set_registers(); |