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| author | Patrick Georgi <patrick.georgi@coresystems.de> | 2009-09-25 18:43:02 +0000 |
|---|---|---|
| committer | Patrick Georgi <patrick.georgi@coresystems.de> | 2009-09-25 18:43:02 +0000 |
| commit | 88f55b2c12f94fd0451902ee2edc663f12e401f4 (patch) | |
| tree | 446179d449934a1dafeb2a2df44b8a515e380807 /src/mainboard/sunw/ultra40/Kconfig | |
| parent | 6bb3bdf869ab06a972520c5a58c6fc9b7cfe99f4 (diff) | |
| download | coreboot-88f55b2c12f94fd0451902ee2edc663f12e401f4.tar.xz | |
some progress on kconfig:
- northbridges are done
- southbridges are done
- Intel CPUs are done, with a design that the board only has to specify
the socket it has, and the CPUs are pulled in automatically. There is
some more cleanup possible in that area, but I'll do that later
- a couple more mainboards compile:
- intel/eagleheights
- intel/jarrell
- intel/mtarvon
- intel/truxton
- intel/xe7501devkit
- sunw/ultra40
- supermicro/h8dme
- tyan/s2850
- tyan/s2875
- via/epia
- via/epia-cn
- via/epia-m
- via/epia-m700
- via/epia-n
- via/pc2500e
(PPC not considered, probably overlooked something)
All of them only _build_, but some options are probably completely
wrong. To be fixed later
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4673 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/sunw/ultra40/Kconfig')
| -rw-r--r-- | src/mainboard/sunw/ultra40/Kconfig | 130 |
1 files changed, 130 insertions, 0 deletions
diff --git a/src/mainboard/sunw/ultra40/Kconfig b/src/mainboard/sunw/ultra40/Kconfig new file mode 100644 index 0000000000..8cdd1f7da9 --- /dev/null +++ b/src/mainboard/sunw/ultra40/Kconfig @@ -0,0 +1,130 @@ +config BOARD_SUNW_ULTRA40 + bool "Ultra40" + select ARCH_X86 + select CPU_AMD_K8 + select CPU_AMD_SOCKET_940 + select NORTHBRIDGE_AMD_AMDK8 + select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX + select SOUTHBRIDGE_NVIDIA_CK804 + select SUPERIO_SMSC_LPC47M10X + select HAVE_PIRQ_TABLE + select USE_PRINTK_IN_CAR + select USE_DCACHE_RAM + help + Sun Ultra40. + +config MAINBOARD_DIR + string + default sunw/ultra40 + depends on BOARD_SUNW_ULTRA40 + +config DCACHE_RAM_BASE + hex + default 0xcf000 + depends on BOARD_SUNW_ULTRA40 + +config DCACHE_RAM_SIZE + hex + default 0x01000 + depends on BOARD_SUNW_ULTRA40 + +config APIC_ID_OFFSET + hex + default 0x10 + depends on BOARD_SUNW_ULTRA40 + +config HAVE_HARD_RESET + bool + default y + depends on BOARD_SUNW_ULTRA40 + +config IOAPIC + bool + default y + depends on BOARD_SUNW_ULTRA40 + +config K8_REV_F_SUPPORT + bool + default n + depends on BOARD_SUNW_ULTRA40 + +config SB_HT_CHAIN_ON_BUS0 + int + default 2 + depends on BOARD_SUNW_ULTRA40 + +config SB_HT_CHAIN_UNITID_OFFSET_ONLY + bool + default n + depends on BOARD_SUNW_ULTRA40 + +config LB_CKS_RANGE_END + int + default 122 + depends on BOARD_SUNW_ULTRA40 + +config LB_CKS_LOC + int + default 123 + depends on BOARD_SUNW_ULTRA40 + +config MAINBOARD_PART_NUMBER + string + default "ultra40" + depends on BOARD_SUNW_ULTRA40 + +config HW_MEM_HOLE_SIZEK + hex + default 0x100000 + depends on BOARD_SUNW_ULTRA40 + +config HAVE_FAILOVER_BOOT + bool + default n + depends on BOARD_SUNW_ULTRA40 + +config USE_FAILOVER_IMAGE + bool + default n + depends on BOARD_SUNW_ULTRA40 + +config MAX_CPUS + int + default 4 + depends on BOARD_SUNW_ULTRA40 + +config MAX_PHYSICAL_CPUS + int + default 2 + depends on BOARD_SUNW_ULTRA40 + +config HT_CHAIN_END_UNITID_BASE + hex + default 0x0 + depends on BOARD_SUNW_ULTRA40 + +config HT_CHAIN_UNITID_BASE + hex + default 0x0 + depends on BOARD_SUNW_ULTRA40 + +config USE_INIT + bool + default n + depends on BOARD_SUNW_ULTRA40 + +config SB_HT_CHAIN_ON_BUS0 + int + default 2 + depends on BOARD_SUNW_ULTRA40 + +config CONSOLE_VGA + bool + default y + depends on BOARD_SUNW_ULTRA40 + +config PCI_ROM_RUN + bool + default y + depends on BOARD_SUNW_ULTRA40 + |