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authorRonald G. Minnich <Ronald G. Minnich>2006-10-13 19:58:52 +0000
committerRonald G. Minnich <rminnich@gmail.com>2006-10-13 19:58:52 +0000
commit4bb8887ac447be339c4e84b03cca681392e48361 (patch)
treed4ba5086400f138d569c6c8ede776cf31985c79d /src/mainboard/sunw/ultra40
parentc34e3ab71e79dc1acf5effcba2830241b2ff7f7e (diff)
downloadcoreboot-4bb8887ac447be339c4e84b03cca681392e48361.tar.xz
change things that make no sense on ultra40. serial output now works!
Signed-off-by: Ronald G. Minnich git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2453 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/sunw/ultra40')
-rw-r--r--src/mainboard/sunw/ultra40/failover.c10
1 files changed, 9 insertions, 1 deletions
diff --git a/src/mainboard/sunw/ultra40/failover.c b/src/mainboard/sunw/ultra40/failover.c
index 537abd43f4..2abd8fc1cd 100644
--- a/src/mainboard/sunw/ultra40/failover.c
+++ b/src/mainboard/sunw/ultra40/failover.c
@@ -23,6 +23,10 @@
#define SUPERIO_GPIO_IO_BASE 0x400
+#define SUPERIO_COM1_DEV PNP_DEV(0x2e, LPC47B397_SP1)
+
+#define SUPERIO_COM1_IO_BASE 0x3f8
+
static void sio_setup(void)
{
@@ -41,11 +45,15 @@ static void sio_setup(void)
pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
#if 1
- lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE);
+ lpc47b397_enable_serial(SUPERIO_COM1_DEV, SUPERIO_COM1_IO_BASE);
+#if 0
+/* what's this?
value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x77);
value &= 0xbf;
lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x77, value);
+*/
+#endif
#endif
}