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| author | Arthur Heymans <arthur@aheymans.xyz> | 2017-03-28 11:50:10 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2017-04-27 10:18:28 +0200 |
| commit | fb2f667da2091ce2194274f95c2d5db024d46e63 (patch) | |
| tree | 5c9c72faf4d1279a5c6b64ca2ae8a1a879ac84aa /src/mainboard/sunw | |
| parent | c0f7a1b7d12062595f01442989e4eac2869e5b7a (diff) | |
| download | coreboot-fb2f667da2091ce2194274f95c2d5db024d46e63.tar.xz | |
nb/amd/amdk8: Link raminit_f.c
For this debug.c needs to be linked too.
Change-Id: I9cd1ffff2c39021693fe1d5d3f90ec5f70891f57
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19030
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/mainboard/sunw')
| -rw-r--r-- | src/mainboard/sunw/ultra40/romstage.c | 8 | ||||
| -rw-r--r-- | src/mainboard/sunw/ultra40m2/romstage.c | 9 |
2 files changed, 8 insertions, 9 deletions
diff --git a/src/mainboard/sunw/ultra40/romstage.c b/src/mainboard/sunw/ultra40/romstage.c index a1659b7f84..7df486a438 100644 --- a/src/mainboard/sunw/ultra40/romstage.c +++ b/src/mainboard/sunw/ultra40/romstage.c @@ -15,7 +15,7 @@ #include <delay.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" -#include "northbridge/amd/amdk8/debug.c" + #include <superio/smsc/lpc47b397/lpc47b397.h> #include <cpu/x86/bist.h> #include "superio/smsc/lpc47b397/early_gpio.c" @@ -26,7 +26,7 @@ #define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT) #define SUPERIO_GPIO_IO_BASE 0x400 -static void memreset(int controllers, const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } #ifdef ENABLE_ONBOARD_SCSI static void sio_gpio_setup(void) @@ -40,9 +40,9 @@ static void sio_gpio_setup(void) } #endif -static inline void activate_spd_rom(const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl) { } -static inline int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); } diff --git a/src/mainboard/sunw/ultra40m2/romstage.c b/src/mainboard/sunw/ultra40m2/romstage.c index 6c3fdbd4e6..576ca6b562 100644 --- a/src/mainboard/sunw/ultra40m2/romstage.c +++ b/src/mainboard/sunw/ultra40m2/romstage.c @@ -34,7 +34,7 @@ #include "northbridge/amd/amdk8/reset_test.c" #include <superio/smsc/dme1737/dme1737.h> #include <cpu/x86/bist.h> -#include "northbridge/amd/amdk8/debug.c" + #include "northbridge/amd/amdk8/setup_resource_map.c" #define SERIAL_DEV PNP_DEV(0x2e, DME1737_SP1) @@ -52,10 +52,10 @@ unsigned get_sbdn(unsigned bus) return (dev >> 15) & 0x1f; } -static void memreset(int controllers, const struct mem_controller *ctrl) { } -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl) { } -static inline int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); } @@ -64,7 +64,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include <northbridge/amd/amdk8/f.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "northbridge/amd/amdk8/raminit_f.c" #include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" |