summaryrefslogtreecommitdiff
path: root/src/mainboard/sunw
diff options
context:
space:
mode:
authorStefan Reinauer <stepan@coresystems.de>2010-04-27 06:56:47 +0000
committerStefan Reinauer <stepan@openbios.org>2010-04-27 06:56:47 +0000
commit14e22779625de673569c7b950ecc2753fb915b31 (patch)
tree14a6ed759e116e9e6e9bbd7f499b74b96d6cc072 /src/mainboard/sunw
parent0e1e8065e303030c39c3f2c27e5d32ee58a16c66 (diff)
downloadcoreboot-14e22779625de673569c7b950ecc2753fb915b31.tar.xz
Since some people disapprove of white space cleanups mixed in regular commits
while others dislike them being extra commits, let's clean them up once and for all for the existing code. If it's ugly, let it only be ugly once :-) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5507 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/sunw')
-rw-r--r--src/mainboard/sunw/Kconfig2
-rw-r--r--src/mainboard/sunw/ultra40/devicetree.cb52
-rw-r--r--src/mainboard/sunw/ultra40/get_bus_conf.c14
-rw-r--r--src/mainboard/sunw/ultra40/irq_tables.c28
-rw-r--r--src/mainboard/sunw/ultra40/mptable.c4
-rw-r--r--src/mainboard/sunw/ultra40/resourcemap.c8
-rw-r--r--src/mainboard/sunw/ultra40/romstage.c22
7 files changed, 65 insertions, 65 deletions
diff --git a/src/mainboard/sunw/Kconfig b/src/mainboard/sunw/Kconfig
index b04d9053c0..8a42be7414 100644
--- a/src/mainboard/sunw/Kconfig
+++ b/src/mainboard/sunw/Kconfig
@@ -1,7 +1,7 @@
choice
prompt "Mainboard model"
depends on VENDOR_SUNW
-
+
source "src/mainboard/sunw/ultra40/Kconfig"
endchoice
diff --git a/src/mainboard/sunw/ultra40/devicetree.cb b/src/mainboard/sunw/ultra40/devicetree.cb
index afa6f66beb..e7917495b7 100644
--- a/src/mainboard/sunw/ultra40/devicetree.cb
+++ b/src/mainboard/sunw/ultra40/devicetree.cb
@@ -7,9 +7,9 @@ chip northbridge/amd/amdk8/root_complex
device pci_domain 0 on
chip northbridge/amd/amdk8 #mc0
device pci 18.0 on end # link 0
- device pci 18.0 on # link1
- # devices on link 0, link 0 == LDT 0
- chip southbridge/nvidia/ck804
+ device pci 18.0 on # link1
+ # devices on link 0, link 0 == LDT 0
+ chip southbridge/nvidia/ck804
device pci 0.0 on end # HT
device pci 1.0 on # LPC
chip superio/smsc/lpc47m10x
@@ -40,29 +40,29 @@ chip northbridge/amd/amdk8/root_complex
end
device pci 1.1 on # SM 0
chip drivers/generic/generic #dimm 0-0-0
- device i2c 50 on end
- end
+ device i2c 50 on end
+ end
chip drivers/generic/generic #dimm 0-0-1
device i2c 51 on end
- end
+ end
chip drivers/generic/generic #dimm 0-1-0
device i2c 52 on end
- end
+ end
chip drivers/generic/generic #dimm 0-1-1
device i2c 53 on end
- end
+ end
chip drivers/generic/generic #dimm 1-0-0
device i2c 54 on end
- end
+ end
chip drivers/generic/generic #dimm 1-0-1
device i2c 55 on end
- end
+ end
chip drivers/generic/generic #dimm 1-1-0
device i2c 56 on end
- end
+ end
chip drivers/generic/generic #dimm 1-1-1
device i2c 57 on end
- end
+ end
end # SM
device pci 1.1 on # SM 1
#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
@@ -71,24 +71,24 @@ chip northbridge/amd/amdk8/root_complex
# end
# chip drivers/generic/generic #PCIXB Slot1
# device i2c 51 on end
-# end
+# end
# chip drivers/generic/generic #PCIXB Slot2
# device i2c 52 on end
-# end
+# end
# chip drivers/generic/generic #PCI Slot1
# device i2c 53 on end
-# end
+# end
# chip drivers/generic/generic #Master CK804 PCI-E
# device i2c 54 on end
-# end
+# end
# chip drivers/generic/generic #Slave CK804 PCI-E
# device i2c 55 on end
-# end
+# end
chip drivers/generic/generic #MAC EEPROM
device i2c 51 on end
- end
+ end
- end # SM
+ end # SM
device pci 2.0 on end # USB 1.1
device pci 2.1 on end # USB 2
device pci 4.0 on end # ACI
@@ -109,18 +109,18 @@ chip northbridge/amd/amdk8/root_complex
register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
register "mac_eeprom_addr" = "0x51"
end
- end # device pci 18.0
+ end # device pci 18.0
device pci 18.0 on end # link 2
device pci 18.1 on end
device pci 18.2 on end
device pci 18.3 on end
end # mc0
-
+
chip northbridge/amd/amdk8
device pci 19.0 on end # link 0
- device pci 19.0 on
+ device pci 19.0 on
# devices on link 1, link 1 == LDT 1
- chip southbridge/nvidia/ck804
+ chip southbridge/nvidia/ck804
device pci 0.0 on end # HT
device pci 1.0 on end # LPC
device pci 1.1 off end # SM
@@ -140,13 +140,13 @@ chip northbridge/amd/amdk8/root_complex
register "mac_eeprom_smbus" = "3"
register "mac_eeprom_addr" = "0x51"
end
- end # device pci 19.0
-
+ end # device pci 19.0
+
device pci 19.0 on end
device pci 19.1 on end
device pci 19.2 on end
device pci 19.3 on end
end
end # PCI domain
-
+
end #root_complex
diff --git a/src/mainboard/sunw/ultra40/get_bus_conf.c b/src/mainboard/sunw/ultra40/get_bus_conf.c
index 53162da97f..8309c8a10f 100644
--- a/src/mainboard/sunw/ultra40/get_bus_conf.c
+++ b/src/mainboard/sunw/ultra40/get_bus_conf.c
@@ -34,7 +34,7 @@
unsigned apicid_ck804b;
unsigned sblk;
-unsigned pci1234[] =
+unsigned pci1234[] =
{ //Here you only need to set value in pci1234 for HT-IO that could be installed or not
//You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
0x0000ff0,
@@ -48,7 +48,7 @@ unsigned pci1234[] =
};
unsigned hc_possible_num;
unsigned sbdn;
-unsigned hcdn[] =
+unsigned hcdn[] =
{ //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most
0x20202020,
0x20202020,
@@ -77,10 +77,10 @@ void get_bus_conf(void)
get_bus_conf_done = 1;
- hc_possible_num = ARRAY_SIZE(pci1234);
-
+ hc_possible_num = ARRAY_SIZE(pci1234);
+
get_sblk_pci1234();
-
+
sbdn = (hcdn[0] & 0xff); // first byte of first chain
sbdn3 = (hcdn[1] & 0xff);
@@ -262,8 +262,8 @@ void get_bus_conf(void)
/*I/O APICs: APIC ID Version State Address*/
#if CONFIG_LOGICAL_CPUS==1
apicid_base = get_apicid_base(4);
-#else
- apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
+#else
+ apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
#endif
apicid_ck804 = apicid_base+0;
apicid_8131_1 = apicid_base+1;
diff --git a/src/mainboard/sunw/ultra40/irq_tables.c b/src/mainboard/sunw/ultra40/irq_tables.c
index 2bbbe7b110..324c87d995 100644
--- a/src/mainboard/sunw/ultra40/irq_tables.c
+++ b/src/mainboard/sunw/ultra40/irq_tables.c
@@ -1,4 +1,4 @@
-/* This file was generated by getpir.c, do not modify!
+/* This file was generated by getpir.c, do not modify!
(but if you do, please run checkpir on it to verify)
Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up
@@ -11,11 +11,11 @@
#include <arch/pirq_routing.h>
#include <cpu/amd/amdk8_sysconf.h>
-static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0,
+static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0,
uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3,
uint8_t slot, uint8_t rfu)
{
- pirq_info->bus = bus;
+ pirq_info->bus = bus;
pirq_info->devfn = devfn;
pirq_info->irq[0].link = link0;
pirq_info->irq[0].bitmap = bitmap0;
@@ -76,15 +76,15 @@ unsigned long write_pirq_routing_table(unsigned long addr)
pirq = (void *)(addr);
v = (uint8_t *)(addr);
-
+
pirq->signature = PIRQ_SIGNATURE;
pirq->version = PIRQ_VERSION;
-
+
pirq->rtr_bus = bus_ck804_0;
pirq->rtr_devfn = ((sbdn+9)<<3)|0;
pirq->exclusive_irqs = 0;
-
+
pirq->rtr_vendor = 0x10de;
pirq->rtr_device = 0x005c;
@@ -100,9 +100,9 @@ unsigned long write_pirq_routing_table(unsigned long addr)
//pcix bridge
write_pirq_info(pirq_info, bus_8131_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
pirq_info++; slot_num++;
-
- if(pci1234[2] & 0xf) {
- //second pci beidge
+
+ if(pci1234[2] & 0xf) {
+ //second pci beidge
write_pirq_info(pirq_info, bus_ck804b_0, ((sbdnb+9)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x0, 0);
pirq_info++; slot_num++;
}
@@ -139,10 +139,10 @@ unsigned long write_pirq_routing_table(unsigned long addr)
//Slot2 pci
write_pirq_info(pirq_info, bus_ck804_1, (0x4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 2, 0);
pirq_info++; slot_num++;
-//nic
+//nic
write_pirq_info(pirq_info, bus_ck804b_0, ((sbdnb+0xa)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
pirq_info++; slot_num++;
-//Slot3 PCIE x16
+//Slot3 PCIE x16
write_pirq_info(pirq_info, bus_ck804b_5, (0<<3)|0, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 3, 0);
pirq_info++; slot_num++;
@@ -162,11 +162,11 @@ unsigned long write_pirq_routing_table(unsigned long addr)
write_pirq_info(pirq_info, bus_8131_1, (4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 6, 0);
pirq_info++; slot_num++;
#endif
-
- pirq->size = 32 + 16 * slot_num;
+
+ pirq->size = 32 + 16 * slot_num;
for (i = 0; i < pirq->size; i++)
- sum += v[i];
+ sum += v[i];
sum = pirq->checksum - sum;
diff --git a/src/mainboard/sunw/ultra40/mptable.c b/src/mainboard/sunw/ultra40/mptable.c
index b019ffea13..be92616e2d 100644
--- a/src/mainboard/sunw/ultra40/mptable.c
+++ b/src/mainboard/sunw/ultra40/mptable.c
@@ -133,7 +133,7 @@ static void *smp_write_config_table(void *v)
}
}
-
+
/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#
*/ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_ck804, 0x0);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, apicid_ck804, 0x1);
@@ -212,7 +212,7 @@ static void *smp_write_config_table(void *v)
//Channel A of 8131
-//Slot 6 PCIX 133/100/66
+//Slot 6 PCIX 133/100/66
for(i=0;i<4;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (4<<2)|i, apicid_8131_1, (0+i)%4); //24
}
diff --git a/src/mainboard/sunw/ultra40/resourcemap.c b/src/mainboard/sunw/ultra40/resourcemap.c
index 726373093f..eae21b4817 100644
--- a/src/mainboard/sunw/ultra40/resourcemap.c
+++ b/src/mainboard/sunw/ultra40/resourcemap.c
@@ -145,7 +145,7 @@ static void setup_ultra40_resource_map(void)
* 1 = base/limit registers i are read-only
* [ 7: 4] Reserved
* [31: 8] Memory-Mapped I/O Base Address i (39-16)
- * This field defines the upper address bits of a 40bit address
+ * This field defines the upper address bits of a 40bit address
* that defines the start of memory-mapped I/O region i
*/
PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
@@ -183,7 +183,7 @@ static void setup_ultra40_resource_map(void)
* [31:25] Reserved
*/
PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x00007000,
- PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x01fff001,
+ PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x01fff001,
PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
@@ -201,7 +201,7 @@ static void setup_ultra40_resource_map(void)
* [ 3: 2] Reserved
* [ 4: 4] VGA Enable
* 0 = VGA matches Disabled
- * 1 = matches all address < 64K and where A[9:0] is in the
+ * 1 = matches all address < 64K and where A[9:0] is in the
* range 3B0-3BB or 3C0-3DF independen of the base & limit registers
* [ 5: 5] ISA Enable
* 0 = ISA matches Disabled
@@ -209,7 +209,7 @@ static void setup_ultra40_resource_map(void)
* from matching agains this base/limit pair
* [11: 6] Reserved
* [24:12] PCI I/O Base i
- * This field defines the start of PCI I/O region n
+ * This field defines the start of PCI I/O region n
* [31:25] Reserved
*/
PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033,
diff --git a/src/mainboard/sunw/ultra40/romstage.c b/src/mainboard/sunw/ultra40/romstage.c
index de16a4481f..76822ce45d 100644
--- a/src/mainboard/sunw/ultra40/romstage.c
+++ b/src/mainboard/sunw/ultra40/romstage.c
@@ -6,7 +6,7 @@
#define SET_NB_CFG_54 1
#endif
-
+
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
@@ -55,7 +55,7 @@ static void sio_gpio_setup(void)
unsigned value;
/*Enable onboard scsi*/
- lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1<<7)|(0<<2)|(0<<1)|(0<<0)); // GP21, offset 0x2c, DISABLE_SCSI_L
+ lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1<<7)|(0<<2)|(0<<1)|(0<<0)); // GP21, offset 0x2c, DISABLE_SCSI_L
value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x4c);
lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(1<<1)));
}
@@ -76,7 +76,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "lib/generic_sdram.c"
/* tyan does not want the default */
-#include "resourcemap.c"
+#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
@@ -111,21 +111,21 @@ static void sio_setup(void)
unsigned value;
uint32_t dword;
uint8_t byte;
-
+
pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xac, 0x047f0400);
-
+
byte = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
- byte |= 0x20;
+ byte |= 0x20;
pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
-
+
dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
dword |= (1<<29)|(1<<0);
pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
-
+
lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE);
-
+
value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x77);
- value &= 0xbf;
+ value &= 0xbf;
lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x77, value);
}
@@ -165,7 +165,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
lpc47b397_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
-
+
/* Halt if there was a built in self test failure */
report_bist_failure(bist);