diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2016-07-30 17:46:17 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-08-14 19:06:25 +0200 |
| commit | 8ab989e31561cea0c6af5d5e242dd2be97bc73b4 (patch) | |
| tree | 31bc3a2175762b179d2fc093c34f62c18b15b9ee /src/mainboard/sunw | |
| parent | 589ef9de8faa2db11a7ce2769fc1d9396a82886b (diff) | |
| download | coreboot-8ab989e31561cea0c6af5d5e242dd2be97bc73b4.tar.xz | |
src/mainboard: Capitalize ROM, RAM, CPU and APIC
Change-Id: Ia1f24d328a065a54975adde067df36c5751bff2d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15987
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/sunw')
| -rw-r--r-- | src/mainboard/sunw/ultra40/get_bus_conf.c | 2 | ||||
| -rw-r--r-- | src/mainboard/sunw/ultra40m2/get_bus_conf.c | 2 | ||||
| -rw-r--r-- | src/mainboard/sunw/ultra40m2/resourcemap.c | 4 | ||||
| -rw-r--r-- | src/mainboard/sunw/ultra40m2/romstage.c | 2 |
4 files changed, 5 insertions, 5 deletions
diff --git a/src/mainboard/sunw/ultra40/get_bus_conf.c b/src/mainboard/sunw/ultra40/get_bus_conf.c index a74048b3ca..4ed57467b4 100644 --- a/src/mainboard/sunw/ultra40/get_bus_conf.c +++ b/src/mainboard/sunw/ultra40/get_bus_conf.c @@ -188,7 +188,7 @@ void get_bus_conf(void) /* CK804b */ - if (pci1234[2] & 0xf) { //if the second cpu is installed + if (pci1234[2] & 0xf) { //if the second CPU is installed bus_ck804b_0 = (pci1234[2] >> 16) & 0xff; #if 0 dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x09, 0)); diff --git a/src/mainboard/sunw/ultra40m2/get_bus_conf.c b/src/mainboard/sunw/ultra40m2/get_bus_conf.c index c70cbec87b..b57f957c60 100644 --- a/src/mainboard/sunw/ultra40m2/get_bus_conf.c +++ b/src/mainboard/sunw/ultra40m2/get_bus_conf.c @@ -79,7 +79,7 @@ static unsigned get_hcid(unsigned i) // we may need more way to find out hcid: subsystem id? GPIO read ? - // we need use id for 1. bus num, 2. mptable, 3. acpi table + // we need use id for 1. bus num, 2. mptable, 3. ACPI table return id; } diff --git a/src/mainboard/sunw/ultra40m2/resourcemap.c b/src/mainboard/sunw/ultra40m2/resourcemap.c index 5235b0d87e..30ce9ea661 100644 --- a/src/mainboard/sunw/ultra40m2/resourcemap.c +++ b/src/mainboard/sunw/ultra40m2/resourcemap.c @@ -265,8 +265,8 @@ static void setup_mb_resource_map(void) * [31:24] Bus Number Limit i * This field defines the highest bus number in configuration region i */ -// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x3f000103, /* link 1 of cpu 0 --> Nvidia MCP55 Pro */ -// PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f400203, /* link 2 of cpu 0 --> nvidia io55 */ +// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x3f000103, /* link 1 of CPU 0 --> Nvidia MCP55 Pro */ +// PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f400203, /* link 2 of CPU 0 --> nvidia io55 */ PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, diff --git a/src/mainboard/sunw/ultra40m2/romstage.c b/src/mainboard/sunw/ultra40m2/romstage.c index 014c3b6e05..7a5ce93319 100644 --- a/src/mainboard/sunw/ultra40m2/romstage.c +++ b/src/mainboard/sunw/ultra40m2/romstage.c @@ -181,5 +181,5 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); - post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now + post_cache_as_ram(); // bsp swtich stack to RAM and copy sysinfo RAM now } |