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| author | Uwe Hermann <uwe@hermann-uwe.de> | 2010-11-21 11:36:03 +0000 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2010-11-21 11:36:03 +0000 |
| commit | 6dc92f0d1a4b6a79c2db800c5bd071daa75a9a23 (patch) | |
| tree | 1b06518d371222763417675b38161d261bd42f93 /src/mainboard/supermicro/h8dme | |
| parent | 86a571797d9ede9d79edcfdce38f50a80b9a49f9 (diff) | |
| download | coreboot-6dc92f0d1a4b6a79c2db800c5bd071daa75a9a23.tar.xz | |
Use DIMM0 et al in lots more places instead of hardocding values.
The (0xa << 3) expression equals 0x50, i.e. DIMM0.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6103 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/supermicro/h8dme')
| -rw-r--r-- | src/mainboard/supermicro/h8dme/romstage.c | 17 |
1 files changed, 9 insertions, 8 deletions
diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c index 86705fdfb6..4f32816ebb 100644 --- a/src/mainboard/supermicro/h8dme/romstage.c +++ b/src/mainboard/supermicro/h8dme/romstage.c @@ -32,6 +32,7 @@ #include <console/console.h> #include <lib.h> +#include <spd.h> #include <cpu/amd/model_fxx_rev.h> @@ -188,15 +189,15 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) */ static const uint16_t spd_addr[] = { // Node 0 - RC0 | (0xa << 3) | 0, RC0 | (0xa << 3) | 2, - RC0 | (0xa << 3) | 4, RC0 | (0xa << 3) | 6, - RC0 | (0xa << 3) | 1, RC0 | (0xa << 3) | 3, - RC0 | (0xa << 3) | 5, RC0 | (0xa << 3) | 7, + RC0 | DIMM0, RC0 | DIMM2, + RC0 | DIMM4, RC0 | DIMM6, + RC0 | DIMM1, RC0 | DIMM3, + RC0 | DIMM5, RC0 | DIMM7, // Node 1 - RC1 | (0xa << 3) | 0, RC1 | (0xa << 3) | 2, - RC1 | (0xa << 3) | 4, RC1 | (0xa << 3) | 6, - RC1 | (0xa << 3) | 1, RC1 | (0xa << 3) | 3, - RC1 | (0xa << 3) | 5, RC1 | (0xa << 3) | 7, + RC1 | DIMM0, RC1 | DIMM2, + RC1 | DIMM4, RC1 | DIMM6, + RC1 | DIMM1, RC1 | DIMM3, + RC1 | DIMM5, RC1 | DIMM7, }; struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE |